A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 .MU.m CMOS A/D Converter for 3G Communication Systems

Kim, Young‐Ju; Lee, Kyung-Hoon; Lee, Myung-Hwan; Lee, Seung‐Hoon

doi:10.1587/transele.e92.c.1194

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…The two input pairs are turned on and off alternately by two slightly overlapped clocks, Q1B and Q2B, to prevent the glitch noise and the settling time delay caused by the two input pairs turning off simultaneously [15]. Meanwhile, the shared amplifier employs a cascode compensation technique to obtain a high phase margin compared to the Miller compensation technique [17]. As a result, the amplifier achieves a phase margin of approximately 55˚ and a wide bandwidth of 220.9 MHz with low power consumption.…”

Section: Shared Amplifier For the Mdad1 And Mdac2mentioning

confidence: 99%

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Park¹,

Jeong²,

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Section: Shared Amplifier For the Mdad1 And Mdac2mentioning

confidence: 99%

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Park¹,

Jeong²,

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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“…The SHA employs the Miller compensation, which is more convenient to satisfy the required bandwidth and phase margin for 150MS/s operation with a zero-nulling resistor. In contrast, the MDACs prefer the cascode compensation for better signal settling behavior, achieving a higher phase margin than the Miller compensation with the same power consumption [6].…”

Section: Proposed Process-insensitive Amplifiermentioning

confidence: 99%

10b 150MS/s 0.4mm<sup>2</sup> 45nm CMOS ADC based on process-insensitive amplifiers

Park

Kim

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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A 10b 150MS/s 0.4mm 2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gainboosting, pseudo-differential output pair, and continuous-time common-mode feedback circuits to overcome various performance limitations that are observed in deep nanometer CMOS technologies. The MDAC2 and MDAC3 share a single high-gain amplifier to reduce the input memory effect, chip area, and power dissipation. The measured DNL and INL are within 1.06 and 1.29LSB, respectively. At 150MS/s, the prototype ADC shows a maximum SNDR of 51.8dB and a maximum SFDR of 63.7dB with a 1.2Vpp sinusoidal input and consumes 47.3mW.

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“…1(a) shows a representative structure of a 2-D current-matrix-based current-steering DAC with a schematic of a 1-bit cell. The structure is good for cell matching owing to the compact current source array, often with common centroid or randomized cell placement [3][4][5]. However, one drawback with this Manuscript received Oct. 6, 2011; revised Jan. 29, 2012.…”

Section: Design Considerations Formentioning

confidence: 99%

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

Kim¹,

Kim²,

Lee³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only 0.0546 mm 2 (0.21 mm x 0.26 mm).

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A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 .MU.m CMOS A/D Converter for 3G Communication Systems

Cited by 11 publications

References 15 publications

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

10b 150MS/s 0.4mm<sup>2</sup> 45nm CMOS ADC based on process-insensitive amplifiers

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

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