A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hwai I.; Wu, Yaping; Huang, Huan-Shun; Lin, Yi-Hsin; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei

doi:10.1109/tcsii.2012.2231017

Cited by 12 publications

(4 citation statements)

References 29 publications

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“…The NVS-WA scheme resembles the negative bit-line (NBL) [6,9,[10][11][12] " .. into LBL to increase V GS and V DS of the pass-gate access transistor, thus improving write-ability. Following the charge sharing write and enabling of the NMOS cross-coupled pair MlIM2 to pull the low-going LBL to GND, NVSL-WA is activated and a negative transient pulsed is coupled into node NVSL (source node of M3), thus introducing a negative below-GND transient pulse at LBL to improve the write ability.…”

Section: Negative Source Line Write-assist (Nvsl-wa)mentioning

confidence: 99%

“…While alternative cells such as 8T cells [2][3][4] have been proposed to lower the SRAM V MIN, the conventional 6T cell remains the mainstream due to its density and speed advantages. Various read/write-assist [5][6][7][8][9][10][11][12] circuits have been actively pursued to mitigate the read-disturb, half select disturb and the conflicting read/write requirements in the conventional 6T cell to lower its V MIN, and low-swing and charging-sharing techniques [13,14] have been employed to reduce the dynamic power and mitigate variability. This paper presents a 256kb 6T SRAM with TPG to facilitate lower NAP mode voltage/power and faster wake-up for the cell array, and low-swing GRBL to reduce the dynamic read power.…”

Section: Introductionmentioning

confidence: 99%

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A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chung

Chang

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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This paper presents a 256kb 6T static random access memory (SRAM) with threshold power-gating (TPG), low swing global read bit-line (GRBL), and charge-sharing write with Vtrip (VTP) tracking and negative source-line (NVSL) write assists (WA). The TPG facilitates lower NAP mode voltage/power and faster wake-up for the cell array, while low-swing GRBL reduces the dynamic read power. A variation-tolerant charge sharing write scheme, where the floating "Low" global write bit line (GWBL) is used to capacitively couple down the local bit-line (LBL), is combined with a cell Vtrip-tracking and NVSL write assists to improve the write-ability. The 256kb test chip is implemented in UMC 40nm low-power (LP) CMOS technology.Error-free full-functionality is achieved from 1.18GHz at 1.5V to 100MHz at 0.65V without redundancy. The TPG scheme reduces the power by 70% (55%) at 1.5V (0.5V) in NAP mode. The low swing GRBL reduces dynamic read power by 3.5% (8%) at 1.IV (0.65V). The VTP-WA and NVSL-WA improve the write V M1N by 50mV (from 0.7V to 0.65V) and reduce write bit failure rate by 2.75x at 0.65V.

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Section: Negative Source Line Write-assist (Nvsl-wa)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chung

Chang

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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“…However, the writeability and write time are degraded owing to their stacked access transistors. Therefore, write assist techniques are required for CP cells to improve the write-ability in low voltage regions [10,11].…”

Section: Introductionmentioning

confidence: 99%

“…However, the write‐ability and write time are degraded owing to their stacked access transistors. Therefore, write assist techniques are required for CP cells to improve the write‐ability in low voltage regions [10, 11]. Nevertheless, the effectiveness of the additional assist circuits is influenced by the process voltage and temperature (PVT) variations as well.…”

Section: Introductionmentioning

confidence: 99%

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

Huang

Chiou

2018

IET Circuits, Devices & Systems

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This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

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A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

et al. 2016

Microelectronics Journal

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A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Cited by 12 publications

References 29 publications

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

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