A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects

Subramaniam, Suryanarayanan; Shinde, Tanmay; Deshmukh, Padmanabh; Shamim, Shahriar; Indovina, Mark; Ganguly, Amlan

doi:10.1109/socc.2017.8226023

Cited by 13 publications

(14 citation statements)

References 12 publications

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“…By reducing the path loss in up to 47 dB, we achieve attenuation levels close to those assumed in recent transceiver proposals (26.5 dB in [36], [37] and 26 dB calculated with data in [38], [39]). Meeting such assumptions would lead to a bit energies of 1.95 pJ/bit for [36], [37] or 0.54 pJ/bit for [38], [39], along the lines of what is assumed in the WNoC literature. On top of that, our transceiver only needs an extra 1.9 dB of SNR to compensate for the ISI effects at 10 Gb/s and BER = 10 −15 .…”

Section: Discussionsupporting

confidence: 79%

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Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Timoneda

Abadal

Franques

et al. 2020

IEEE Trans. Commun.

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Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions are far from realistic by evaluating losses and dispersion in commercial chips. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce losses by 47 dB and dispersion by 7.3×, enabling intrachip wireless communications over 10 Gb/s and only 1.9 dB away from the dispersion-free case.

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Section: Discussionsupporting

confidence: 79%

“…To make an explicit connection between channel losses and efficiency, we note that power amplifiers are the most consuming components of current transceivers, e.g., 70.8% in [38], [39]. Compensating for extra losses, noise figures, or circuit limitations would make these figures to increase even further.…”

Section: Discussionmentioning

confidence: 99%

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Timoneda

Abadal

Franques

et al. 2020

IEEE Trans. Commun.

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Section: Ghz Receivermentioning

confidence: 99%

“…Here, we discuss a 60 GHz receiver proposed in [68] that can demodulate the signal received over inter-chip wireless interconnect transmitted from the above the transmitter. The Figure 5b shows the components of the receiver that consists of a high gain Low Noise Amplifier (LNA) and an OOK demodulator to demodulate the amplified received signal.…”

Section: Ghz Receivermentioning

confidence: 99%

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Ganguly

Ahmed

Narde

et al. 2018

JLPEA

Self Cite

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With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

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“…Due to its potential, WNoCs have been investigated extensively from different standpoints [7]- [9]. At the circuit level, most efforts have focused on the design of the analog front end [6] or aspects around it, e.g., power gating [10]. In contrast, and despite being a critical function in any wireless system, data conversion has been generally overlooked or taken for granted.…”

Section: Introductionmentioning

confidence: 99%

Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case

Abadal

Alarcón

2018

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

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Network-on-Chip (NoC) is currently the paradigm of choice to interconnect the different components of Systemon-Chips (SoCs) or Chip Multiprocessors (CMPs). As the levels of integration continue to grow, however, current NoCs face significant scalability limitations and have prompted research in novel interconnect technologies. Among these, wireless intra-chip communications have been under intense scrutiny due to their low latency broadcast and architectural flexibility. Thus far, the practicality of the idea has been studied from the RF frontend and the network interface perspectives, whereas little to no attention has been placed on another essential component: the data converters. This article aims to fill this gap by providing a comprehensive analysis of the requirements of the scenario, as well as of the current performance and cost trends of Analogto-Digital Converters (ADCs). Based on Murmann's data, we demonstrate that ADCs will not be a roadblock for the realization of wireless intra-chip communications although current designs do not meet their demands fully.

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A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects

Cited by 13 publications

References 12 publications

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case

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