A 0.4-to-30 GHz CMOS Low Noise Amplifier With Input-Referred Noise Reduction and Coupled-Inductive-Peaking Technique

Hai-tang, Dong; Wang, Keping; Yang, Geliang; Ma, Shiyue; Ma, Kaixue

doi:10.1109/lmwt.2023.3268096

IEEE Microw. Wireless Tech. Lett.

2023

DOI: 10.1109/lmwt.2023.3268096

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A 0.4-to-30 GHz CMOS Low Noise Amplifier With Input-Referred Noise Reduction and Coupled-Inductive-Peaking Technique

Dong Hai-tang

Keping Wang

Geliang Yang

et al.

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Cited by 9 publications

(2 citation statements)

References 11 publications

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“…To extend the bandwidth of the LNA, various techniques have been reported [1][2][3][4][5][6]. In [1], a passive matching network with two inductors is placed at the input of LNA to achieve broadband input matching.…”

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confidence: 99%

“…The passive matching network of two inductors at the input increases the chip area and deteriorates noise figure (NF). The inductor-resistor series peaking technique was proposed to expand the gain bandwidth in [2,3], but this technique consumes part of the DC voltage and degrades the linearity performance of the LNA. Broadband matching based on magnetically coupled resonator technology has also been recently proposed and is often used for wideband inter-stage matching [4,5].…”

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confidence: 99%

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A sub‐6GHz wideband low noise amplifier with high gain and low noise figure in 110‐nm SOI CMOS

Wang,

Li,

2023

Electronics Letters

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This letter presents a sub‐6 GHz wideband low noise amplifier (LNA) based on a double L‐type load network and utilizes the negative feedback technique. Using the cascode structure, along with the aforementioned techniques, it is possible to achieve a single‐stage wideband LNA with high gain and low noise figure (NF). Fabricated in 110‐nm SOI CMOS technology, the proposed LNA achieves a maximum power gain of 15.2 dB, noise figure of 1.0–1.56 dB. The 3‐dB bandwidth ranges from 3.05 to 4.55 GHz. The minimum power input at 1 dB compression point (IP1dB) is −17.1 dBm. The LNA area is 0.18 mm2 and dissipates a total power of 11.5 mW from a 1.4‐V power supply.

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confidence: 99%

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confidence: 99%

A sub‐6GHz wideband low noise amplifier with high gain and low noise figure in 110‐nm SOI CMOS

Wang,

Li,

2023

Electronics Letters

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Design of distributed impedance‐matching networks for ultra‐wideband low‐noise amplifiers

Kim

2024

Micro & Optical Tech Letters

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An ultra‐wideband low‐noise amplifier (LNA) design was developed based on distributed network synthesis to achieve impedance matching of an active device by parasitic absorption. The equivalent device models of a low‐noise device were generated using negative‐image device modeling and traveling‐wave matching, and matching circuits were produced using the Chebyshev approximation. The minimum insertion loss and ripple of the matching networks were adjusted correctly to allow the parasitic absorption to match the device models. This paper describes the design methodology for distributed matching circuits and its application to the design of an ultra‐wideband LNA.

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A high-gain wideband balun-LNA with multiple noise-optimized technique

Li,

Zhang,

Wei

et al. 2024

AEU - International Journal of Electronics and Communications

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A 0.4-to-30 GHz CMOS Low Noise Amplifier With Input-Referred Noise Reduction and Coupled-Inductive-Peaking Technique

Cited by 9 publications

References 11 publications

A sub‐6GHz wideband low noise amplifier with high gain and low noise figure in 110‐nm SOI CMOS

A sub‐6GHz wideband low noise amplifier with high gain and low noise figure in 110‐nm SOI CMOS

Design of distributed impedance‐matching networks for ultra‐wideband low‐noise amplifiers

A high-gain wideband balun-LNA with multiple noise-optimized technique

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