A 0.44-<i>μ</i>J/dec, 39.9-<i>μ</i>s/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

Dbouk, Hassan; Gonugondla, Sujan K.; Sakr, Charbel; Shanbhag, Naresh R.

doi:10.1109/jssc.2020.3029586

Cited by 18 publications

(7 citation statements)

References 17 publications

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“…Table II compares the performance of our KWS IC with other state-of-the-art KWS ICs [2], [6], [9], [38], [39]. This work uses an on-chip analog FEx while other works needed an off-chip high-resolution (16-bit) ADC [6], [38].…”

Section: Measurement Resultsmentioning

confidence: 99%

“…This work uses an on-chip analog FEx while other works needed an off-chip high-resolution (16-bit) ADC [6], [38]. Sometimes even the digital FEx and ADC were implemented off-chip [39]. Furthermore, only this work and [2] support the essential "Unknown" class to be detected as a distinct class, which is the most challenging class in the GSCD test set.…”

Section: Measurement Resultsmentioning

confidence: 99%

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A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

Kim

Gao²,

Graça³

et al. 2022

IEEE J. Solid-State Circuits

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This article presents the first keyword spotting (KWS) IC which uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front-end. Benefiting from fundamental building blocks based on digital logic gates, it offers a better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65 nm CMOS process, the prototyped KWS IC occupies 2.03mm 2 and dissipates 23 µW power consumption including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves 54.89 dB dynamic range for 16 ms frame shift size while consuming 9.3 µW. The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command Dataset (GSCD) with >86% accuracy and 12.4 ms latency.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

Kim

Gao²,

Graça³

et al. 2022

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…In this comparison, this work consumes less power than other works with similar model architecture [2], [5], [6] even though we process the entire raw data for the predicted results. [3], [4] use RNN as the model architecture, but [3] does not include feature extraction on the chip.…”

Section: ) Results and Comparisonmentioning

confidence: 99%

“…Another key point of this work is that we combine the IMC architecture for higher energy efficiency. [3], [4] also uses inmemory computing and [5], [6] uses approximate computation that is also an analog domain computation for lower power consumption. [2] is the full digital design counterpart for a similar application.…”

Section: ) Results and Comparisonmentioning

confidence: 99%

“…Zheng et al [2] proposes a binary neural network-based design with on-chip self-learning to update the entire model. Dbouk et al [3] uses recurrent attention network and hybrid digital and multibit in-memory computing for ultra low power KWS. Guo et al [4] proposes hybrid digital circuits and 16 64x64 SRAM-based in-memory computing (IMC) macros with 3-bit ADC for recurrent neural network-based KWS.…”

Section: Introductionmentioning

confidence: 99%

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A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization

Chiang

Chang

Jou

2022

IEEE Trans. VLSI Syst.

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Keyword spotting has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always-on nature and the variety of speech, it necessitates a low-power design as well as user customization. This paper describes a low-power, energy-efficient keyword spotting accelerator with SRAM based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and nonideal effects. To address the issues mentioned above, this paper proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this paper proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that with user customization, we can recover the accuracy loss from 51.08% to 89.76% with compensation and fine-tuning and further improve to 96.71% with customization. The chip implementation can successfully run the model with only 14uJ per decision. When compared to the state-of-the-art works, the presented design has higher energy efficiency with additional on-chip model customization capabilities for higher accuracy.

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Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector

Yang

Zhu

Shan

2021

2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting

Cited by 18 publications

References 17 publications

A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction

A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization

Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector

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