A 0.5 V high-speed comparator with rail-to-rail input range

Kandala, Mallik; Wang, Haibo

doi:10.1007/s10470-012-9898-4

Cited by 12 publications

(5 citation statements)

References 13 publications

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“…14 In the circuit, all the NMOS devices are zero-Vt devices and meanwhile PMOS devices are low-V t devices. Simulations in Ref.…”

Section: Design Techniques For Rail-to-rail Comparatorsmentioning

confidence: 99%

“…Second, when the transistors in the NIC and PIC circuits have dramatically di®erent transconductances, their sizes are also quite di®erence and the capacitive loads at the two sub comparator outputs will be di®erent, which also helps restrain the delay di®erences. Equation (14) also indicates that the proposed design can be optimized such that its delay is insensitive to input common mode voltage V in;CM . On one hand, when V in;CM is high, the NMOS input pair of the NIC circuit is more e®ectively conducting and hence the NIC circuit initial voltage V out1 ð0Þ is large.…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…Following this trend, several comparators with rail-to-rail input range have been reported in literature. [12][13][14] However, the reported designs either su®er signi¯cant performance degradation in ultra-low voltage operation or require the use of zero-V t devices, which may not be universally available in all CMOS (Complementary Metal Oxide Semiconductor) technologies. This paper presents a new rail-torail comparator design that can be implemented with using regular V t devices and is signi¯cantly faster than existing rail-to-rail designs in low-voltage operation.…”

Section: Introductionmentioning

confidence: 99%

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Design Techniques for Ultra-Low Voltage Comparator Circuits

Wang

2014

J CIRCUIT SYST COMP

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This paper presents a novel low-voltage rail-to-rail comparator circuit and derives optimal transistor size ratios for both conventional latch-based and the proposed comparators which operate in transistor subthreshold region. The obtained analytical results serve well as guidelines for designing low-voltage comparators and the proposed circuit is signi¯cantly faster than existing rail-to-rail comparator designs in ultra-low voltage operation.

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“…14 In the circuit, all the NMOS devices are zero-Vt devices and meanwhile PMOS devices are low-V t devices. Simulations in Ref.…”

Section: Design Techniques For Rail-to-rail Comparatorsmentioning

confidence: 99%

Section: Circuit Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design Techniques for Ultra-Low Voltage Comparator Circuits

Wang

2014

J CIRCUIT SYST COMP

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“…The comparator resolution is determined both by its sensitivity, i.e., the minimum voltage difference that can be detected, and by the offset. A further important feature in many applications is the input common-mode range (ICMR): some ADC architectures (e.g., exploiting single-ended signals [35,36], or SAR ADCs based on the set-and-down algorithm [37]) require a rail-to-rail ICMR to allow a comparison of signal levels across the whole input range [36,[38][39][40].…”

Section: Introductionmentioning

confidence: 99%

“…Several latched comparators have been proposed in the literature that can operate with supply voltages of 0.5 V and lower [21,24,30,31,41,42]. They are often based on the StrongARM architecture [17][18][19][20][25][26][27]38,43,44], where a differential pair with a clocked tail current generator is loaded by a pair of cross-coupled inverters that form a latch. The ultra-low-voltage (ULV) operation is often achieved by substituting the inverters with simple PMOS devices [28,34,[45][46][47], cross-coupled in positive feedback, or by exploiting body driving.…”

Section: Introductionmentioning

confidence: 99%

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Sala

Spinogatti

Bocciarelli

et al. 2023

JLPEA

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In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.

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A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

Khanghah¹,

Sadeghipour

2013

Analog Integr Circ Sig Process

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A 0.5 V high-speed comparator with rail-to-rail input range

Cited by 12 publications

References 13 publications

Design Techniques for Ultra-Low Voltage Comparator Circuits

Design Techniques for Ultra-Low Voltage Comparator Circuits

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

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