A 0.5-V low power analog front-end for heart-rate detector

Suda, Naveen; Nishanth, P; Basak, Debajit; Sharma, Durshee; Paily, Roy

doi:10.1007/s10470-014-0402-1

Cited by 16 publications

(3 citation statements)

References 27 publications

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“…This stage provides a high differential and differential gain for single-ended switching. The second stage consists of the p-channel load current M6 and the nchannel common-source amplifier MS [8]. The MS and M9AAe semiconductors provide a bias for the op-amp circuit.…”

Section: The Implementation Of Operating Amplifiermentioning

confidence: 99%

Using Lt Spice Tools, Design and Perform a First-Order Sigma-Delta Modulator Simulation

2023

IJPREMS

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Also proposed is a fully absolute sigma-delta ADC based on the form and modeling of a high-gain, two-power operational amplifier enabled by 90 nm nanotechnology and a switched capacitor with a first-order modulator. Both of these devices are based on 90nm nanotechnology. A low-power, high-efficiency, first-order, 1-bit sigma-delta ADC with a bandwidth of 10MHz. This circuit converts analog indicators to digital. A single-digit sigma-delta (L-1") first request modulator has been designed, rebuilt, evaluated, and decided to be robust using a state-of-the-art 1.8V LTspice CMOS 250nm power supply. Comparative Simulation Sigma A low-power, small-area, and traditional A/D converter is simulated to demonstrate that Delta gives superior performance.

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Section: The Implementation Of Operating Amplifiermentioning

confidence: 99%

Using Lt Spice Tools, Design and Perform a First-Order Sigma-Delta Modulator Simulation

2023

IJPREMS

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“…The recent years have seen an ever-increasing diffusion of novel and smart electronic applications, pervading all aspects of daily life. Many fields of applications have been completely rethought thanks to the ever increasing inno-vation of biomedical [1,2,3,4] and Internet of Things (IoT) apparatuses such as portable and wearable devices, and smart sensors [5]. These architectures demand for low power consumption, to extend battery life or to be able to operate on harvested energy sources.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Voltage class-AB OTA exploiting local CMFB and Body-to-Gate interface

Centurelli

Sala

Monsurrò

et al. 2022

AEU - International Journal of Electronics and Communications

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“…The rapid advancement of CMOS technologies has forced the modern consumer electronics market towards growing sophistication of applications powered by batteries in our daily life such as cell phones, laptops, micro-sensor nodes, wireless sensor networks, and portable medical devices through the appropriation of low power design techniques [1][2][3][4][5][6][7]. This trend has invigorated the attention in the evolution of low voltage and low power analog and mixedsignal ICs for growing battery-operated applications.…”

Section: Introductionmentioning

confidence: 99%

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

Ghosh

Bhadauria

2021

Analog Integr Circ Sig Process

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An efficient architecture of a high-performance ultra-low-voltage gate-driven two-stage pseudo-fully differential operational transconductance amplifier (OTA) is presented. The proposed subthreshold-region operated OTA utilizes two identical conventional current-mirror-based source coupled pseudo-differential amplifiers with their cross-connected gate as core amplifier blocks. The input core differential pair exploiting forward body terminal biasing scheme at output load employed in cascaded stages essentially improves the overall transconductance more than twice compared to the conventional pseudo-differential pair based OTA and achieves near rail-to-rail output voltage swing (90.2% of supply voltage) for near rail-to-rail input common-mode voltage (94.92% of supply voltage). The circuit is designed and optimized using g m /I D technique associated with the Particle Swarm Optimization (PSO) algorithm with a single supply of 0.35 V for a capacitive load of 10 pF and simulated in Cadence Virtuoso analog environment using UMC 180-nm CMOS technology. Post-layout simulations have been accomplished to justify the performance of the proposed OTA. It achieves an open-loop gain of 83.00 dB, phase margin of 61.48°, and power dissipation of 35.04 nW at a unity gain frequency of 24.78 kHz. A low-frequency continuous second-order G m -C filter is also implemented to validate its workability. Simulation results of this work are compared to the state-of-the-art architecture available, and enhanced performance is validated. Keywords Operational transconductance amplifier (OTA) Á Unity gain frequency (UGF) Á Subthreshold region Á Input common-mode range (ICMR) Á Biquad G m -C filter & Sougata Ghosh

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A 0.5-V low power analog front-end for heart-rate detector

Cited by 16 publications

References 27 publications

Using Lt Spice Tools, Design and Perform a First-Order Sigma-Delta Modulator Simulation

Using Lt Spice Tools, Design and Perform a First-Order Sigma-Delta Modulator Simulation

An Ultra-Low-Voltage class-AB OTA exploiting local CMFB and Body-to-Gate interface

An ultra-low-power near rail-to-rail pseudo-differential subthreshold gate-driven OTA with improved small and large signal performances

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