A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS

Abstract

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter "doubles" the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of −106 dBc/Hz [figure of merit (FoM) of −239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop.

A Time Synchronized Multi-Hop Mesh Network with Crystal-Free Nodes

“…The RF crystal and corresponding PLL, on the other hand, can burn significant power. Even in recent work, such as [4], the power consumption of the frequency synthesis alone is over 1 mW from a 0.5 V supply, which is comparable to the power consumption of the entire system-on-chip used in this paper. The high power consumption is because of high-frequency divider and high-speed phase comparison, both of which can consume significant energy, albeit over very short periods of time if the radio is heavily duty-cycled.…”