A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression

Ultra-low power signal processor for biomedical applications

“…FAERDC along with a proposed extension method and a near-threshold operation have been applied in LP (including GP) as a sample popular hardware accelerator. The LP has been fabricated in 180 nm CMOS technology and its functionality is verified at 0.5 V. We have published these works in [23], [24], [25], [26].…”