A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications

Song, Yan; Xue, Zhongming; Xie, Yi; Fan, Shiquan; Geng, Li

doi:10.1109/tcsi.2016.2528080

Cited by 41 publications

(18 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The SAR ADC produced an ENOB equals to 9.5-bit. This result shows good performance of SAR ADC comparatively with previous work in [22][23][24][25][26].…”

Section: Figure 10 Sar Adc Digitized Outputsupporting

confidence: 55%

“…Thus, the impedance of the amplifier test setup is presented in Figure 5. Then, input resistance (R IN ) is determined by using (5). 5The value of recommended resistor can be referred to in AD8139 data sheet [17].…”

Section: Figure 3 Adr8139 Test Setupmentioning

confidence: 99%

“…The SAR ADC can be characterized by three types of input stage that depend on device functionality, namely, single ended, pseudo differential and fully differential. Fully differential SAR ADC input has advantage in rejecting commonmode noise and interference and increase system performance due to balanced input signal [4][5][6]. It also offers double dynamic analog voltage input range compared to single ended input.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Differential input range driver for SAR ADC measurement setup

Yusuf

Shafie

Majid

et al. 2020

IJEECS

View full text Add to dashboard Cite

<span>Differential successive approximation register (SAR) of analog to digital converter (ADC) requires two balancing input signals that have same amplitude with 180⁰ out of phase. Otherwise, it performs inaccurately and degrades the performance during ADC testing procedure. Therefore, an implementation of AD8139 chip single to differential amplifier was chosen as an ADC driver to generate sufficient differential output for the ADC. The chip was placed on a printed circuit board (PCB) to test the functionality as well as the performance of static and dynamic SAR ADC. The result shows that the single-ended input transform into differential voltage outputs. The amplitudes for the amplifier remain equal and is 180° out of phase for DC and AC voltage input signal. Besides, the fabricated 0.18µm CMOS technology of differential 10-bit SAR ADC is capable of digitising full code digital output and perform 9.5-bit effective number of bit (ENOB) from analog input driving by the ADC driver.</span>

show abstract

“…The SAR ADC produced an ENOB equals to 9.5-bit. This result shows good performance of SAR ADC comparatively with previous work in [22][23][24][25][26].…”

Section: Figure 10 Sar Adc Digitized Outputsupporting

confidence: 55%

Section: Figure 3 Adr8139 Test Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Differential input range driver for SAR ADC measurement setup

Yusuf

Shafie

Majid

et al. 2020

IJEECS

View full text Add to dashboard Cite

show abstract

“…These two shortcomings make the conventional flash ADC unsuitable for SoC systems. Several recent designs that have smaller area have been reported such as those in other studies 6–36 …”

Section: Problem Statement and Previous Workmentioning

confidence: 99%

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

Abdalla

2020

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary The analog‐to‐digital converters (ADCs) play a very important role in electronic products, radar, communication systems and signal processing, to name such a few. In this paper, a novel all‐metal‐oxide semiconductor (MOS) flash‐like analog‐to‐digital converter (FLADC) that consists of five stages is proposed. The design was performed using only MOS transistors, and the proposed ADC works in a way similar to the conventional flash ADC. According to the proposed ADC, there is no need for the comparators used in the conventional flash ADCs, thus resulting in a reduction in both the transistor count and the power consumption. The sound operation and the superiority of the proposed ADC compared to previous works is verified by simulation using the 0.13‐μm complementary MOS (CMOS) technology with a power‐supply voltage, VDD, of 1.2 V. The simulation has been conducted on a 5‐bit FLADC that is built by 276 MOS transistors only which is approximately 32% of the transistor count of the corresponding conventional flash ADC and has no resistors. According to the simulation results, the proposed 5‐bit FLADC consumes 3.23 mW at sampling rate of 0.5 GS/s.

show abstract

“…The Successive Approximation Register (SAR) ADC as a candidate is reported as the most power efficient ADC structure. Nevertheless, as the resolution of the SAR ADCs are increased, these structures become bulky and the mismatch problem in the DAC would be more serious [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Rikan

Kim

Ahmad

et al. 2018

Sensors

View full text Add to dashboard Cite

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

show abstract

A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications

Cited by 41 publications

References 23 publications

Differential input range driver for SAR ADC measurement setup

Differential input range driver for SAR ADC measurement setup

A novel flash‐like all‐metal‐oxide semiconductor analog‐to‐digital converter suitable for system on chips systems

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR

Contact Info

Product

Resources

About