A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

Zhu, Dezheng; Chen, Chao; Zhao, Yan; Peng, Chenglei; Cai, Zhikuang

doi:10.1587/elex.18.20200441

Cited by 1 publication

(1 citation statement)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…High-performance CP design is another challenge under the low voltage supply, the reference spur is mainly induced by the non-ideal effects of CP and phase and frequency detector (PFD) circuit. In general, the cascode operation amplifier and negative feedback technique are used to guarantee the charging and discharging current matching in the conventional charge pump circuit [16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]. However, the threshold voltage does not decrease with the voltage supply [30], resulting in the efficient operating voltage range of the charge pump becoming narrower.…”

Section: Introductionmentioning

confidence: 99%

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

Chen

2022

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

This paper presents a low-power fractional-N synthesizer for BLE with a gate-switching charge pump (CP) and high-speed prescaler. To reduce the current mismatch under low supply voltage, a master-slave rail-to-rail operational trans-conductance amplifier (OTA) structure is employed to the CP; Current self-matching technique guarantees the charging current is equal to discharging current. The embedded logic gates and power switch technique are employed to true-single-phase-clock (TSPC) to reduce power consumption and improve the operating speed of the divider. Random dither is injected into the ∆Σ modulator to prolong the period of output sequence. The proposed phase-locked loop (PLL) is implemented in the 40-nm CMOS process. It achieves −85.94 dBc/Hz@100 kHz and −109.18 dBc/Hz@1 MHz in fractional-N mode while consuming 1.6 mW under a 0.7 V voltage supply.

show abstract