A 0.7 V, 40 nW Compact, Current-Mode Neural Spike Detector in 65 nm CMOS

Abstract

In this paper, we describe a novel low power, compact, current-mode spike detector circuit for real-time neural recording systems where neural spikes or action potentials (AP) are of interest. Such a circuit can enable massive compression of data facilitating wireless transmission. This design can generate a high signal-to-noise ratio (SNR) output by approximating the popularly used nonlinear energy operator (NEO) through standard analog blocks. We show that a low pass filter after the NEO can be used for two functions-(i) estimate and cancel low frequency interference and (ii) estimate threshold for spike detection. The circuit is implemented in a 65 nm CMOS process and occupies 200 μm × 150 μ m of chip area. Operating from a 0.7 V power supply, it consumes about 30 nW of static power and 7 nW of dynamic power for 100 Hz input spike rate making it the lowest power consuming spike detector reported so far.

Towards Intelligent Intra-cortical BMI (i2BMI): Low-power Neuromorphic Decoders that outperform Kalman Filters

“…15 and transmitter power dissipation was found by multiplying data rate to reported transmitter power efficiency of 3.775 nJ/bit [8]. In the firing rate computation block, only spike detection block was considered for simplicity with 40 nW/channel [15] power consumption. Finally, SELMA was employed as a decoder considering reasonably large number of hidden layer neurons, L = 1500, Analog M ACs = 15 × 10 6 , Digital M ACs = 15 × 10 3 , Energy/(Analog M AC) = 0.45 pJ [21], Energy/(Digital M AC) = 10 pJ [55].…”

Experimental Comparison of Hardware-Amenable Spike Detection Algorithms for iBMIs

“…The underlying hypothesis is that NEO helps in better spike detection which in turn leads to enhanced performance. Thus, based on previous simulation studies [15], [16], current results and hardware amenability [17] we advocate switching from AT to NEO as the de facto spike detection method. Future work includes closed-loop trials and applying NEO in conjunction with more sophisticated decoders such as neural networks and Kalman filters.…”

“…Firstly, it is restricted to just one NHP instead of the standard protocol of two NHPs. Secondly, the proposed method's hardware implementation consumes up to three orders of magnitude more power than the ones reported for NEO [17], [18], [21] reflecting it's computational complexity.…”

“…The value of l is optimized as per the experimental conditions [16], [21] and is not as sensitive as AT due to better spike to noise separation. Other methods of automatic threshold setting that are less sensitive to amplitude of the NEO output can also be used [17]. Also, NEO can be applied directly to the analog signals after the amplifier and before the ADC to save the ADC power dissipation [17].…”

“…Other methods of automatic threshold setting that are less sensitive to amplitude of the NEO output can also be used [17]. Also, NEO can be applied directly to the analog signals after the amplifier and before the ADC to save the ADC power dissipation [17].…”