A 0.7-V 870-$\mu$W Digital-Audio CMOS Sigma-Delta Modulator

Low-power sigma-delta modulator with half-sample delayed-input feedforward

“…In this simulation, the input frequency is at the edge of signal bandwidth, 312.5 kHz, for oversampling ratio of 64. As the input power increases the integrator output swing remain nearly constant and small as expected in (3), (4). With a −6-dB input at 100 kHz, the output spectrum of the modulator is shown in Fig.…”

“…Another approach, shown in Fig. 2, to extending the processing time in the feedback path is to introduce a one-sample delay in the input feedforward path [4]. Although the signal component at the input of the first integrator is not completely removed in this architecture, its magnitude is attenuated by the (L+1)th order, where L is the order of the modulator.…”

“…The nonidealities introduced by the added delay in the input feedforward path are attenuated by the noise shaping provided by the feedback. However, for implementing the added delay it requires additional switched-capacitor circuits that are controlled by an extra clock generator [4].…”

“…(1) the signal transfer function is not unity but has a high-pass filtering characteristic, as in [4]. However, its magnitude is nearly flat and unity over the z-domain frequencies up to 0.1, and then increases to 7 as the frequency Fig.…”

“…4. The major difference compared to [4] is that no additional circuitry is needed to implement the added delay in the input feedforward path on the assumption that the actual circuit is differential and the polarity inversion from modulator input to quantizer input, denoted as ÀV IN in the half-sample delayed-input feedforward, is realized by simply applying negative modulator input to the quantizer. While the negative input is sampled onto C 1 during sampling phase, when È 1 and È 1d are high, the charge sampled onto C OS during the previous integration phase is transferred to the preamplifier by grounding node X.…”