A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology

Lo, Yu-Lung; Chen, Wei-Jen

doi:10.1016/j.mejo.2012.07.008

Cited by 9 publications

(3 citation statements)

References 24 publications

(38 reference statements)

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“…In recent years, the technology trend in biomedical engineering have tremendously increased the market demand for portable, wearable and implantable devices [1][2][3]. The requirement on complete functional integration semiconductor chip such as Silicon-on-Chip (SoC) in low power environment has becoming more important [4]. The advanced in transistor process technology that continuously required for a lower supply voltage with limited power consumption budget has put circuit designer into formidable challenges, especially the power management module [5,6].…”

Section: Introductionmentioning

confidence: 99%

A low quiescent current low dropout voltage regulator with self-compensation

Lee¹,

Sidek²,

Sulaiman³

et al. 2019

Bulletin EEI

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This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.

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Section: Introductionmentioning

confidence: 99%

A low quiescent current low dropout voltage regulator with self-compensation

Lee¹,

Sidek²,

Sulaiman³

et al. 2019

Bulletin EEI

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show abstract

“…The LDO in [15] with 100 nF off-chip output capacitor can deliver only 200 μA current to the load while consuming 2.7 μA quiescent current, considering an array of 256 power transistors. On the other hand, [16] shows a digitally controlled LDO regulator in which the output voltage variation and settling time to the load transient are quite large, namely 700 mV and 1.77 ms, respectively. The quiescent current of the LDO in [17] with off-chip output capacitor of 4.5 nF is 164.5 μA that can discharge fast the battery voltage.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, recently, some digital LDOs have been reported in [15][16][17]. The LDO in [15] with 100 nF off-chip output capacitor can deliver only 200 μA current to the load while consuming 2.7 μA quiescent current, considering an array of 256 power transistors.…”

Section: Introductionmentioning

confidence: 99%

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

Saberkari

Qaraqanabadi

Shirmohammadli

et al. 2015

Circuit Theory & Apps

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SUMMARYThis article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxidesemiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18 μm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on-chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

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Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

Yang

Lin

2017

Circuits Syst Signal Process

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A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology

Cited by 9 publications

References 24 publications

A low quiescent current low dropout voltage regulator with self-compensation

A low quiescent current low dropout voltage regulator with self-compensation

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

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