A 0.8 mm² Sub-GHz GaAs HBT Power Amplifier for 5G Application Achieving 57.5% PAE and 28.5 dBm Maximum Linear Output Power

Abstract

This paper presents a comprehensive design of a fully integrated multistage GaAs HBT power amplifier that achieves both linearity and high efficiency within a chip area of 0.855 mm 2 for 4G and 5G applications covering the lower frequency band of 700-800 MHz. A novel linearizer circuit is integrated to a dual stage class-AB PA to minimize the AM-PM (Amplitude Modulation-Phase Modulation) distortion generated by the parasitic capacitance at the PN-junction under low bias current condition. The linearized power amplifier is able to operate within a 100 MHz linear operating bandwidth (700-800 MHz) while meeting the adjacent channel leakage ratio (ACLR) specification for 4G and 5G application. The fully integrated PA achieves a wideband efficiency of 57.5% at 28.5 dBm output power. Observing a respective input and output return losses of less than 13 dB and 10 dB, the PA delivers a power gain within the range of 34.0-37.0 dB across the operating bandwidth while exhibiting an unconditional stability characteristic from DC up to 5 GHz. The proposed linearization method paves the way of reducing the complexity of linear and high efficiency PA design which is associated with complicated and high-power consumption linearization schemes.

Sustainable Macromolecular Materials in Flexible Electronics

“…In today's communication technologies, while the need for bandwidth and fast communication elements is accommodated in our lives with 5G, [ 63 ] teraHertz studies have accelerated with 6G studies. It is now necessary to design communication devices with high switching capability or to operate devices close to the visible light wavelength.…”

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

“…With CMOS technology, the most challenging block in an RF transceiver is the power amplifier. On the other hand, PAs using III-V compound semiconductor technology typically provide a higher output power with high efficiency because of the low breakdown voltage of the transistor and a lossy substrate of CMOS, degrading the performance of the designed PAs [7][8][9]. Thus, when considering commercial applications, the design of an internal CMOS PA needs to include the operation of an optional external PA [10][11][12][13].…”

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

“…CMOS technology has been has attracted significant attention in integrated circuit design due to its low cost of implementation and to achieve the goal of realizing complete system-on-chip (SoC) implementation. CMOS-based PAs have numerous limitations because of their low breakdown voltage, the low-quality factor of passive components, high silicon-substrate loss, and the inaccessibility of back via holes for the ground, in which they restrict the attainable linear output power and efficiency as compared to III-V based PAs such as Gallium Arsenide (GaAs) and Gallium Nitride (GaN)-based PAs [ 1 , 2 , 3 , 4 ]. Myriad performance-improving methods for linearity and efficiency refinement have been implemented for CMOS PAs to address these aforementioned limitations [ 5 , 6 ].…”