A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity

Liu, Shubin; Ji, Yaling; Liao, Xufeng; Qin, Zhenghe; Liang, Hongzhi

doi:10.1109/tvlsi.2022.3140457

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2024

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Cited by 9 publications

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“…The phase noise of a phase-locked loop (PLL) is a crucial metric for assessing the quality of the clock generated by the PLL [3]. Therefore, designing low-phase-noise oscillators and charge pumps is key to achieving a low-phase-noise PLL [4].…”

Section: Introductionmentioning

confidence: 99%

A charge pump phase-locked loop with low phase noise based on ring oscillator

Guo,

Qin,

2024

J. Phys.: Conf. Ser.

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This paper presents a low-phase-noise charge pump phase-locked loop (PLL) based on a ring oscillator. It uses a 4-stage ring oscillator to provide orthogonal signals and exhibit a phase noise of -102 dBc/Hz at a carrier offset of 1 MHz. When powered by a 1.2 V DC supply, the static current of the PLL is less than 4 mA. The PLL is driven by a 40 MHz clock source and outputs a square wave at 2.56 GHz, with a phase noise of -94.8 dBc/Hz at 1 MHz offset. The circuit is implemented using a 55 nm CMOS process, with a final layout area of only 0.06 mm2.

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Section: Introductionmentioning

confidence: 99%