A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

Won, Hyosup; Yoon, Taehun; Han, Jinho; Lee, Joon-Yeong; Yoon, Jong-Hyeok; Kim, Sang Woo; Lee, Jeongsup; Lee, Sangeun; Han, Kwangseok; Lee, Jin‐Hee; Park, Jinho; Bae, Hyeon‐Min

doi:10.1109/jssc.2014.2369494

Cited by 27 publications

(8 citation statements)

References 26 publications

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“…Following the IEEE 802.3 standard specifications, several 100 Gb/s links are already in production [40], [49], [50] as a 4x25 Gb/s parallel link. A shortwave WDM (SWDM) alliance has been established to multiplex different wavelengths near 850nm from multiple VCSELs on a single fiber pair [51], [6].…”

Section: Towards a Power Efficient Tera-bit/s Linkmentioning

confidence: 99%

Silicon-Photonics Microring Links for Datacenters—Challenges and Opportunities

Ahmed

Sharkia

Casper

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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The rapid growth of warehouse-scale datacenters demands high-throughput optical interconnects that can span short-to-medium reach distances (< few kilometers). Microringbased silicon-photonics links with single mode fibers (SMFs) are highly promising for these applications. This paper presents an analysis of microring-based links from the holistic perspective of optical devices, CMOS circuits, and system-level link budget and energy-efficiency simulations. Design considerations and tradeoffs for the receiver, transmitter and the overall link are presented, and comparisons are made to the mainstream multimode vertical-cavity surface-emitting laser (VCSEL)-based links with multi-mode fibers (MMFs). Finally, research opportunities are highlighted for further improving the energy efficiency of single-channel and wavelength division multiplexing (WDM)based silicon-photonics links.

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Section: Towards a Power Efficient Tera-bit/s Linkmentioning

confidence: 99%

Silicon-Photonics Microring Links for Datacenters—Challenges and Opportunities

Ahmed

Sharkia

Casper

et al. 2016

IEEE J. Select. Topics Quantum Electron.

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“…However, sometimes it is impossible for users to select a COTS chip that satisfies all their requirements. For instance, limited by system power consumption, some industrial applications require chip power to be less than 1W to substitute the original Ethernet low-power chip [7]. As COTS TSN chips installed many unnecessary functionalities for these applications, there is no COTS chip that satisfies this low-power requirement, as far as we know.…”

Section: Introductionmentioning

confidence: 99%

Fenglin-I: An Open-Source Time-Sensitive Networking Chip Enabling Agile Customization

Quan

Yan

et al. 2023

IEEE Trans. Comput.

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Time-Sensitive Networking (TSN) technology is experiencing diverse application requirements and forming a complicated standard system. It is extremely difficult to design a one-fits-all chip for all TSN applications. Therefore, application-driven TSN chip customization is inevitable. Generally, chip customization starts from a "clean-slate". For complicated ASIC chips, that results in significant development overhead. Inspired by RISC-V chips, an open-source template will significantly reduce the customization complexity. Along this road, we propose an open-source TSN chip named Fenglin-I. Fenglin-I includes a high-level abstraction to build a relationship between application requirements and chip implementation, source code of a real chip named FastTSN to provide reference code for chip implementation, and software tools to facilitate chip verification. Based on Fenglin-I, we further propose a TSN chip customization method that provides step-by-step guidance about customizing TSN chips agilely. To verify the effectiveness of Fenglin-I and the proposed customization method, we use FPGA arrays to prototype and verify FastTSN. The results show that FastTSN achieves microsecond-level transmission jitter for unicast and multicast time-critical traffic. Additionally, we demonstrate two domain-specific TSN chip customization cases in which the customized chips reuse at least 84% of FastTSN code while meeting their requirements.

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“…Scaling I/O bandwidth while maintaining the area-, energyefficiency is challenging due to channel equalization. Typical transceivers in the wireline serial links include power-hungry equalizers to cancel out pre-, post-cursors caused either by inter-symbol interference (ISI) or reflection [4], [5], [7]- [10]. If an effective equalizer cannot be designed, a forward errorcorrection (FEC) block is used to achieve the error-free link performance at the cost of latency.…”

Section: Introductionmentioning

confidence: 99%

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

Lee

Kim

Park

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In convolutional neural network (CNN) accelerators, the dominant power consumption is caused by the access of external data memory. In addition, power and area occupied by I/O interfaces maintaining low bit-error-rate, e.g., 1e-15, grow as the data rate increases. Considering the inherent error resilience of the inference process in machine learning applications, the requirement of error-free communication in the data-path is controversial. In this paper, a custom CNN accelerator integrating a channel emulator is designed by using an FPGA to analyze the effect of the BER of an I/O transceiver on the image classification accuracy. In order to implement a channel emulator, a digital-domain look-up-table (LUT)-based 12-tap FIR filter is employed to create inter-symbol interference (ISI), and a PRBS31 generator is used as a noise source. The implementation was evaluated by running the ImageNet dataset on the FPGA-based custom accelerator (Virtex Ultrascale+) implementing VGG-16. The results show that the BER up to 1e-4 in the memory access has a negligible impact on the inference accuracy.

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A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

Cited by 27 publications

References 26 publications

Silicon-Photonics Microring Links for Datacenters—Challenges and Opportunities

Silicon-Photonics Microring Links for Datacenters—Challenges and Opportunities

Fenglin-I: An Open-Source Time-Sensitive Networking Chip Enabling Agile Customization

Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators

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