A 0.8V 8-bit low-power asynchronous level-crossing ADC with programmable comparison windows

Li, Yongjia; Duan, Zhao; Serdijn, Wouter A.

doi:10.1109/biocas.2013.6679658

Cited by 6 publications

(6 citation statements)

References 6 publications

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“…The LNA is optimized for noise efficiency [24] and distortion while the PGA is optimized for driving the capacitive SAR-ADC, adjusting the gain. A simple way to utilize level-crossing sampling is replacing the capacitive SAR-ADC with a capacitive LC-ADC like the ones in [11]- [15]. However, as mentioned in Section I, there are leakage related issues associated with capacitive structures at low frequency applications.…”

Section: System Designmentioning

confidence: 97%

“…In other words, the SNDR we obtained from the LC-ADC output is the SNDR of the whole system. In line with previous works [12], [15], a logic analyzer was used in the measurements to count the time in between the asynchronous samples. Signal reconstruction and interpolation were performed in MATLAB utilizing polynomial interpolation.…”

Section: Measurementsmentioning

confidence: 99%

“…As there are only few fully integrated systems with level-crossing sampling for biomedical applications, this inspired us to design the whole readout front-end and apply it to biomedical signal recording. This work is a follow-up of previous work [15], but with the entire readout system integrated on a single chip. The recently published LC-ADCs [6]- [15] can be divided into different categories.…”

mentioning

confidence: 94%

“…This work is a follow-up of previous work [15], but with the entire readout system integrated on a single chip. The recently published LC-ADCs [6]- [15] can be divided into different categories. First, based on how the level crossing is detected, there are floating-window and fixed-window structures.…”

mentioning

confidence: 94%

“…So it is not practical to use the capacitive DAC in a LC-ADC for applications in which the input frequency can be as low as mHz. The LC-ADC in previous works [12], [15] was implemented with a single-bit capacitive-feedback DAC and fixed-window detection, leading to considerable power savings. However, when the input signal lowers to Hz or sub-Hz, the capacitive DACs are not able to hold the input signal for a long time, resulting in dramatic SNDR degradation.…”

mentioning

confidence: 99%

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An ECG Recording Front-End With Continuous-Time Level-Crossing Sampling

Mansano

Yuan³

et al. 2014

IEEE Trans. Biomed. Circuits Syst.

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An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

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Section: System Designmentioning

confidence: 97%

Section: Measurementsmentioning

confidence: 99%

mentioning

confidence: 94%

mentioning

confidence: 94%

mentioning

confidence: 99%

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An ECG Recording Front-End With Continuous-Time Level-Crossing Sampling

Mansano

Yuan³

et al. 2014

IEEE Trans. Biomed. Circuits Syst.

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A Low-power Level-Crossing ADC for Biosignal Acquisition

Lin

Chen

2023

J. Phys.: Conf. Ser.

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A large number of redundant signals will be generated when the traditional Nyquist sampling method is used to acquire a biological signal, leading to a system’s energy loss. A new level-crossing analog-to-digital converter (LC-ADC) with non-uniform sampling and fixed window structure is presented, with fewer data and low power consumption features. The circuit uses a 6-bit capacitive DAC to quantize the input signal, avoiding the error accumulation of the 1-bit capacitive DAC structure, and a nanoamp CMOS current bias circuit to provide a very low quiescent current for the comparator, further reducing power consumption. The structure was verified in a 0.18μm CMOS technology. The results indicate that the total power dissipation is 0.26uw@500Hz, the signal-to-noise distortion ratio (SNDR) is 59dB@500Hz, and ENOB reached 9.51bit, which is suitable for the acquisition of low-frequency biological signals.

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High precision clockless ADC using wavelet neural network

El-Masry

El-Dib

2016

2016 28th International Conference on Microelectronics (ICM)

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A 0.8V 8-bit low-power asynchronous level-crossing ADC with programmable comparison windows

Cited by 6 publications

References 6 publications

An ECG Recording Front-End With Continuous-Time Level-Crossing Sampling

An ECG Recording Front-End With Continuous-Time Level-Crossing Sampling

A Low-power Level-Crossing ADC for Biosignal Acquisition

High precision clockless ADC using wavelet neural network

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