A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

Zhao, Haoyi; Dai, Fa Foster

doi:10.1109/isscc42614.2022.9731702

Cited by 6 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…SAR-Assisted digital slope ADCs in prior art use a monotonic switching scheme on a single branch, the other branch remaining at a fixed voltage [7]- [8]. Consequently, the discharging operation is always in the same direction.…”

Section: A Unidirectional Digital Slopementioning

confidence: 99%

“…However, precise matching between then VTC and Time to digital converter (TDC) time constants is needed in such an approach. Conceptually similar architectures [7]- [8] propose to use a delay-line driven digital slope (DS) with 1-LSB steps as second stage, combining the discharge of the residue and the time-to-digital conversion into a single operation. The state of the delay-line at zero crossing of the digital slope represents the output code in thermometric representation.…”

Section: Introductionmentioning

confidence: 99%

“…Both implementations apply the digital slope on the positive branch only of the differential circuit in monotonic switching, requiring to first level shift the SAR residue to the positive domain. Limiting the bandwidth of the comparator has the effect of time interpolation between consecutive steps which can increase the achievable resolution by up to 3 bits [8]. This paper presents a 2 step SAR Assisted ADC with a pseudo-differential approach allowing a bidirectional digital slope.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

Casanova

Perrin

Nicolas

2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

This paper presents a novel architecture of a SAR assisted 2 step ADC where the SAR residue is quantized with a bidirectional digital slope time-based converter. The bidirectional slope halves the conversion time of the second stage. Furthermore, the redundancy requirements in the second stage are considerably reduced through a unified global calibration scheme. A practical example is given for a 12-bit 64 MS/s ADC with 67 dB SNDR and 208 µW estimated power consumption targeted at ultra-low power RF receivers. The complete architecture including calibration has been validated with VerilogA models including capacitor mismatch, comparator offsets and noise.

show abstract

Section: A Unidirectional Digital Slopementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

Casanova

Perrin

Nicolas

2023

2023 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…While Refs. [174,175] taking advantage of the outstanding energy efficiency of Pipe-SAR ADC at the large signal swing in the voltage domain, it switches the fine conversion in the time domain to maintain the efficiency at a low supply voltage (half of regular V DD ). The 13 b ADC [174] design running at 20 MS/s achieves 182.4 dB FoM S and the 12 b ADC samples at 260 MS/s with 171.8 dB FoM S , as marked in Fig.…”

Section: Pipeline Hybrid Adcsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

View full text Add to dashboard Cite

For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

show abstract

“…In ultrasonic water meter applications, TDC circuit detects the time difference between forward and reverse ultrasonic emission to obtain information such as flow rate and temperature. In TDC-based ADC circuits, higher accuracy and better linearity are obtained by quantifying the charging time of the capacitor [4]. Therefore, resolution, range, and power consumption are critical parameters for TDC circuits.…”

Section: Introductionmentioning

confidence: 99%

Design of high-resolution and wide-range time-to-digital converter

Wang¹,

Wu²

2023

Eighth International Conference on Electronic Technology and Information Science (ICETIS 2023)

View full text Add to dashboard Cite

Time digital conversion technology has been widely used in the field of measurement technology. A high-resolution, widerange Time-to-Digital-Converter (TDC) circuit is proposed based on Multiplier Delay-Locked Loop (MDLL) and Time Amplifier (TA). In this paper, a two-segment combination structure is adopted to obtain a wide range by using the cycle counting method in the high segment, and to take into account the high resolution by using the time amplification technique in the middle and low segments. Finally, a TDC circuit with a range of 500 ps ~ 4 us and a resolution of 18 ps is presented.

show abstract

A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

Cited by 6 publications

References 3 publications

A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

A Very Low Power 12 bit 64-MS/s 2 step SAR Assisted Bidirectional Digital Slope ADC

Trending IC design directions in 2022

Design of high-resolution and wide-range time-to-digital converter

Contact Info

Product

Resources

About