A 0.9V CMOS 3-5 Ghz broadband flat gain low-noise amplifier for ultra-wide band receivers

A 3–6 GHz Current Reused Noise Canceling Low Noise Amplifier for WLAN and WPAN Applications

“…Finally, for the input return loss, 1 % of samples at 3 GHz frequency have the maximum deviation between 0.1 and 0.2 dB. Table 2 provides a benchmark performance comparison of the proposed LNA with some recent works [8,16,27,28]. As it can be seen, the proposed LNA has the maximum flat power gain and the best linearity characteristic with a proper noise figure and input/ output return losses over the entire frequency range, while its power dissipation is quite lower than that in [8,16,28] and is comparable with [27].…”

Design of low power UWB LNA for frequency 3.1–5 GHz in 0.18 μm CMOS technology

“…C gs ║L s at input and L2║C gs2 at the output are resonating simultaneously. The input transistor M 1 width is 120μm for proper input matching and Vb is set at 0.5 V to ensure that M1 is in saturation region [1] [5]. In common-source amplifier and source follower, the input signal is applied to the gate of the MOSFET.…”

“…The size of M 4 is used as a cascade device is chosen to be smaller than other transistor and it is relative size is smaller than the other transistor which results in decreasing the noise figure and parasitic capacitance [1]. The transistor M 2 has been added in parallel with M 1 to increase the gain and linearity.…”

“…1.Common source and common gate transistor M 1 and M 2 are connected in parallel [3]. The output stage of LNA consist from common source transistor M 3 and M 4 using cascading topology to obtain the maximum gain [1].…”

A 1-V noise cancelling CMOS differential LNA for UWB applications

“…This issue can be alleviated by employing an inductor instead of a resistor. Since this can limit input matching, the effects of the input transistor channellength modulation have been considered, leading to improved input matching [10]. As a future trend, UWB mandates to integrate both digital and analog parts with less complexity, consequently decreasing the analog power supply to sub 1 − V to merge both supplies of analog and digital together is crucial.…”