A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

Ahn, Hyun-A; Sung, Yoo-Chang; Kim, Yong-Hun; Kim, Janghoo; Kim, Kihan; Lee, Donghun; Go, Young-Gil; Lee, Jae-Woo; Jung, Jae-Woo; Kim, Yong-Hyun; Choi, Ga-Ram; Park, Jun-Seo; Lee, Bo-Hyeon; Baek, Jinhyeok; Moon, Daesik; Lim, Daihyun; Bae, Seung-Jun; Sohn, Young-soo; Yoo, Changsik; Oh, Tae-Young

doi:10.1109/a-sscc58667.2023.10348005

2023 IEEE Asian Solid-State Circuits Conference (A-Sscc) 2023

DOI: 10.1109/a-sscc58667.2023.10348005

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A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

Hyun-A Ahn,

Yoo-Chang Sung,

Yong-Hun Kim

et al.

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A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

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