A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET

Tajalli, Armin; Bastani, Mohammad Hassan; Carnelli, Dario Albino; Cao, Chen; Fox, Josef J.; Gharibdoust, Kiarash; Gorret, Davide; Gupta, Amit Kumar; Hall, Charles E.; Hassanin, Ahmed H.; Hofstra, Klaas L.; Holden, Brian; Hormati, Ali; Keay, John; Mogentale, Yohann; Paul, Goutam; Perrin, Victor; Phillips, J.A.; Raparthy, Sumathi; Shokrollahi, Amin; Stauffer, D.; Simpson, R.; Stewart, Andrew; Surace, Giuseppe; Amiri, Omid Talebi; Truffa, Emanuele; Tschank, Anton; Ulrich, R.; Walter, Christoph; Singh, Anant

doi:10.23919/vlsic.2019.8778172

Cited by 4 publications

(2 citation statements)

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“…As the signal rate increases, the BER also increases. Therefore, in order to solve this problem, the matrix A is used for row transformation (13) which significantly improves the SNR when the information of the signal is not lost. FIGURE 6: Encoding and decoding eye diagrams Fig.…”

Section: Cnrz-7mentioning

confidence: 99%

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

et al. 2022

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A novel high-speed transceiver based on 7 bit correlated non-return-to-zero(CNRZ-7) with high-bandwidth-density(bandwidth per unit length) and low-power for Die-to-Die(D2D) communication is proposed. In order to further improve the SNR and the bandwidth of the CNRZ-5 in D2D communication, a CNRZ-7 based transmitter matrix and receiver matrix are proposed firstly, which are derived from Walsh Hadamard(W-H) transform and inverse transformation. In addition, to reduce the power consumption of the transmitter, the encoding driver based on CNRZ-7 transmitter matrix is designed with source series terminated drivers(SST). To further improve the SNR of the receiver, the decoding circuit based on CNRZ-7 receiver matrix is designed with a special multi-input comparators(MIC), which contain equalizer circuits. This transceiver is designed with a 28nm CMOS technology and the core area is 0.66mm 2 . The postsimulation results show that this transceiver can operate at 280 Gb/s, and the data rate is 35 Gb/s/wire. The worst width of the receiver's eye-diagrams is 0.45UI when the transceiver operates at a 50 mm PCB channel with a 10dB@20GHz insertion loss, and the total BER is less than 1E-15. The power consumption is 1.1pJ/b under a normal corner.INDEX TERMS Wireline transceiver, correlated non-return-to-zero(CNRZ), Walsh Hadamard, SST, MIC, D2D communication, pin efficiency.

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Section: Cnrz-7mentioning

confidence: 99%

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication

et al. 2022

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“…The MINI-PLL adjusts the phase of the PI, so that the clock generated by the VCO is sampled to the best position of the data. CDA is used to process the phase early/late information and send it to the PI [4,13].…”

Section: Receiver Designmentioning

confidence: 99%

A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

2022

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This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed data paths and a pair of low-speed differential clocks for 512 Gbps BW. To reduce the chip area and power consumption, a common minimal phase-locked loop (MINI-PLL) and data adjustment (CDA) circuit to replaces the clock data recovery circuit (CDR) in the traditional receiver. A delay-matching circuit is adopted to combat PVT variation and lane skew. In addition, a high linearity phase interpolator (PI) circuit design is used in the minimum phase-locked loop (MINI-PLL) to adjust the clock phase and improve the clock jitter performance. Using 28 nm CMOS technology, the overall link power consumption is 1.56 pJ/b. Bit error rate (BER) is less than 10−15 under the real S-parameters with a channel loss of 10db@16GHz.

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