A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Kim, Dongkyun; Kim, Yongmi; Lee, Dong Uk; Lee, Jaein; Kwon, Kihun; Choi, Byeongchan; Kim, Hongjung; Ku, Sanghyun; Kim, Jong-Sam; Oh, Seung-Wook; Park, Minsu; Im, Dain; Lee, Yong-Sung; Choi, Jong‐Min; Chun, Junhyun; Jin, Kyo-Won; Jang, Sungchun; Song, Jianwei; Chi, Hankyu; Choi, Geun-Ho; Choi, Sunmyung; Kim, Changhyun; Han, Minsik

doi:10.1109/jssc.2019.2948806

Cited by 18 publications

(3 citation statements)

References 12 publications

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“…The tap weights CP and CN are analog values, which are set by an external 5-b digital code through a DAC. In memory interfaces, the adaptation is performed through the memory controller due to limited area [26]. In the initialization and the periodic re-training between the memory and its controller, the controller can calculate and update the tap weights of the TD-DFE again.…”

Section: Transition-detecting Decision Feedback Equalizermentioning

confidence: 99%

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A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

et al. 2021

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The signal integrity of dual-rank LPDDR5 interface is challenged by reflections from the stub of the inactive rank within the redistribution layer (RDL). These reflections arrive at the active rank within the unit-interval of the data-rate and distort not only the post-cursor but also the pre-cursor of the signal that the decision feedback equalizer (DFE) cannot remove. We introduce a differentiating receiver that restores data through edge information to eliminate the reflective distortions, including the pre-cursor, and a transition-detecting DFE to address remaining inter-symbol interference. A prototype receiver, fabricated in a 65 nm CMOS process, eliminates pre-cursor distortion with a reflection flight time of 50 ps

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Section: Transition-detecting Decision Feedback Equalizermentioning

confidence: 99%

“…To measure the BER bathtub curves, we manually adjusted the clock-data delay with a signal quality analyzer. In a real system, a memory interface has training sequences to align the clock to the center of data [26]. With the proposed receiver, the horizontal opening of the eye is improved by 0.360 UI at 6.4 Gb/s with a 12mm stub.…”

Section: Clock Pathmentioning

confidence: 99%

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

et al. 2021

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“…The PRDLL uses phase interpolation to adjust the clock phase from 0 to 2 π. Since the delay line is short, the cumulative clock jitter of the PRDLL is less than that of a NAND-based DLL, and the ILO can achieve low jitter [13]. Based on PRDLL, Hyunsu Park aligned the rising edges of the input clock and output gated clock using on-chip divided sampling clocks and proposed a direct input-output comparison technique to minimize the use of replica delay lines [14].…”

Section: Introductionmentioning

confidence: 99%

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

et al. 2023

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This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

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A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface

Lee

2022

IEEE Access

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A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

Cited by 18 publications

References 12 publications

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

A Single-Ended Transmitter With Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface

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