A 1.2-ns HEMT 64-kb SRAM

Suzuki, M.; Notomi, S.; Ono, Masaaki; Kobayashi, Naoki; Mitani, Eizo; Odani, K.; Mimura, Takashi; Abe, Masayuki

doi:10.1109/4.98974

Cited by 25 publications

(6 citation statements)

References 8 publications

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“…To demonstrate the performance of the cell a 8-words x 4bits prototype was fabricated using Vitesse III -GaAs technology. A die photo of this experimental circuit is shown in Fig 11. The layout of prototype, including bonding pads, occupies an area of 1.15 mm 2 . The test chip was tested at a power supply voltage of 1V and 2V.…”

Section: Resultsmentioning

confidence: 99%

“…Much effort has been dedicated to the development of GaAs SRAMs and some remarkable progress in power reduction, performance and temperature tolerance have been obtained [1] [2]. Recently, more emphasis has been placed on lowpower, high-speed rather than large memory capacity, primarily led by cache applications in high speed microprocessors.…”

Section: Introductionmentioning

confidence: 99%

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A new low-power GaAs two-single-port memory cell

Bernal

Guyot

1998

IEEE J. Solid-State Circuits

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This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36*37 mu m/sup 2/ using a 0.6- mu m technology. An experimental 32 word * 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word*4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 mu A/cell when operated at 1 V

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new low-power GaAs two-single-port memory cell

Bernal

Guyot

1998

IEEE J. Solid-State Circuits

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“…12) HEMT 1 k, 4 k and 64 kbit static random-access memory (SRAM) chips were successfully developed. [13][14][15] The main factors that made such advances possible are as follows: First, the current-gain cutoff frequency f T of the HEMT is much higher than that of conventional devices because of the superior transport properties of the HEMT channel. Second, the HEMT structure has an inherently large channel aspect ratio (gate length to distance between the gate and 2DEG at the heterointerface), facilitating scaling down of the device without significant short-channel effects.…”

Section: Integrated Circuits For High-speed Systemsmentioning

confidence: 99%

Development of High Electron Mobility Transistor

Mimura

2005

Jpn. J. Appl. Phys.

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“…Instead, TSRAM RTDs are optimized for very low current-density NDR characteristics and high capacitance (low speed index). A III-V record low standby power (50 nW/bit, compared with about 20 µW/bit in [65]) TSRAM gain cell using three heterostructure field-effect transistors (HFETs) and two RTDs has recently been demonstrated [1,2]. This design removes the drawback of the high standby power of RTDbased Goto-type [66] SRAM cells [23,24,26].…”

Section: Introductionmentioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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A 1.2-ns HEMT 64-kb SRAM

Cited by 25 publications

References 8 publications

A new low-power GaAs two-single-port memory cell

A new low-power GaAs two-single-port memory cell

Development of High Electron Mobility Transistor

Tunnelling-based SRAM

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