A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

Kundu, Sandipan; Lu, Julia Hsin-Lin; Alpman, Erkan; Lakdawala, Hasnain; Paramesh, Jeyanandh; Jung, Byunghoo; Zur, Sarit; Gordon, E.

doi:10.1109/cicc.2014.6945992

Cited by 12 publications

(8 citation statements)

References 11 publications

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“…The individual SAR ADC presented in this work achieves one of the best efficiencies for sampling rates around 100 MS/s with the process used. Moreover, the efficiency is comparable to the designs reported in previous studies, [27][28][29] where much more advanced CMOS process nodes are used.…”

Section: Test Chip Measurementssupporting

confidence: 76%

“…Previous studies 12,18,26,30 are implemented in the same process node that the work introduced here, but they achieve worse FoM and operate at much lower sampling rate. The designs presented in previous studies 28,31,32 achieve better efficiency, although they are fabricated in newer and power-optimized process nodes. However, the sampling rates in pevious studies 28,31 are significantly lower.…”

Section: Test Chip Measurementsmentioning

confidence: 99%

“…The designs presented in previous studies 28,31,32 achieve better efficiency, although they are fabricated in newer and power-optimized process nodes. However, the sampling rates in pevious studies 28,31 are significantly lower. Finally, the high-speed circuits in Chung et al 32 require a 1.5 V source to operate properly.…”

Section: Test Chip Measurementsmentioning

confidence: 99%

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A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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This paper presents the design, implementation, and measurements of a 4 GS/s, 8-bit resolution, time-interleaved (TI) analog-to-digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI-ADC in the process used. An energy-efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on-chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low-voltage differential signaling interface is included to transmit the samples off-chip without any decimation. The TI-ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv-step and owing to the efficient interleaved architecture the full TI-ADC achieves a peak FOM of 171fJ/conv-step (526fJ/conv-step at Nyquist).

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Section: Test Chip Measurementssupporting

confidence: 76%

Section: Test Chip Measurementsmentioning

confidence: 99%

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A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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“…To demonstrate the viability of SLIC, several projects have been initiated [19][20][21][22][23][24][25][26][27][28][29][30][31][32]. A brief overview of some of these projects, which span from applications, architectures, and circuits, are presented here in this section.…”

Section: Slic Projectsmentioning

confidence: 99%

Statistical learning in chip (SLIC)

Blanton¹,

Li²,

Mai³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Self Cite

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Despite best efforts, integrated systems are "born" (manufactured) with a unique 'personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the bestperforming systems but this would result in unacceptable yields and correspondingly high costs. The system personality is further shaped by its environment (e.g., temperature, noise and supply voltage) and usage (i.e., the frequency and type of applications executed), and since both can fluctuate over time, so can the system's personality. Systems also "grow old" and degrade due to various wear-out mechanisms (e.g., negative-bias temperature instability), and unexpectedly due to various early-life failure sources. These "nature and nurture" influences make it extremely difficult to design a system that will operate optimally for all possible personalities. To address this challenge, we propose to develop statistical learning in-chip (SLIC). SLIC is a holistic approach to integrated system design based on continuously learning key personality traits on-line, for selfevolving a system to a state that optimizes performance hierarchically across the circuit, platform, and application levels. SLIC will not only optimize integrated-system performance but also reduce costs through yield enhancement since systems that would have before been deemed to have weak personalities (unreliable, faulty, etc.) can now be recovered through the use of SLIC.

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“…Since the offset and gain mismatches are static errors, their corrections are straightforward and simple, and they can be estimated by giving DC reference voltage to the input of the ADC during the calibration period [26]. In contrast, the time skew mismatch is relatively difficult to correct because the skew-induced error is dependent on signal content [6,27].…”

Section: Self-calibration Techniquementioning

confidence: 99%

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

et al. 2019

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A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

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A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

Cited by 12 publications

References 11 publications

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Statistical learning in chip (SLIC)

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

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