A 1.2-V 77-dB 7.5-MHz Continuous-Time/Discrete-Time Cascaded &amp;#x003A3;&amp;#x00394; Modulator

Kulchycki, S.D.; Trofin, Roxana; Vleugels, K.; Wooley, B.A.

doi:10.1109/vlsic.2007.4342733

Cited by 6 publications

(1 citation statement)

References 2 publications

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“…2. This quantization error can be used in different loop architectures such as the MASH structure [14], [15] or time-interleaved noise-coupled structures [16], [17], without the need for an extra DAC to extract this quantization error. The rest of this section discusses the implementation of the proposed quantizer in a delta-sigma modulator loop.…”

Section: Noise-shaped Quantizer In Delta-sigma Loopmentioning

confidence: 99%

A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer

Maghari

Moon

2011

IEEE J. Solid-State Circuits

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This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation. With a small modification to the discharging phase of the dual-slope ADC, first-order quantization noise shaping is achieved. This quantizer is used in a second-order loop filter and results in an overall third-order quantization noise shaping. To remove the need for any extra active element, this quantizer is merged with the active adder. In this fashion, the multi-bit flash ADC is removed and hence the loading of the active-adder is reduced to a single continuous-time comparator. Furthermore, to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements, a bi-directional discharging scheme is proposed. As a proof of concept, the second-order loop filter with the proposed quantizer is fabricated in a 0.18 m CMOS technology and achieves over 78 dB SNDR with an oversampling ratio of 24 and 50 MHz sampling speed. The power consumption is 2.9 mW from a 1.5 V power supply.

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