A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

Liu, Bangan; Ngo, Huy Cu; Nakata, Kengo; Deng, Wei; Zhang, Yuncheng; Qiu, Junjun; Yoshioka, Torn; Emmei, Jun; Zhang, Haosheng; Pang, Jian; Narayanan, Aravind Tharayil; Yang, Dongxu; Liu, Hanli; Okada, Kei; Matsuzawa, Akira

doi:10.1109/cicc.2018.8357041

Cited by 20 publications

(10 citation statements)

References 7 publications

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“…PLLs. Many different DTC implementations have been devised, such as constant-slope (CS) [34]- [38], variableslope (VS) [39]- [42], and path-selection (PS) based topologies [10], [19], [43], [44]. Considering the feasibility of standard cell implementation, VS and PS DTCs are preferred.…”

Section: Multi-stage Fully-synthesizable Dtc Dtcs Have Found Extensive Usage In High Performancementioning

confidence: 99%

“…Therefore, the nonlinearity of a fabricated DTC can be expressed as in PLLs and MDLLs [19], [39], [48]. In this work, the proposed synthesizable DTC nonlinearity is dominated by random mismatches, instead of the architectural nonlinearity [10]. Therefore, the conventional PWLI is modified in two ways to accommodated the mismatch-dominated DTC, which is summarized in Table I.…”

Section: B Nonlinearity Analysismentioning

confidence: 99%

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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu

Zhang

Qiu

et al. 2021

IEEE Trans. Circuits Syst. I

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In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48 ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than −59.0 dBc, and the reference spur is −64.5 dBc. The power consumptions are 1.85 mW and 1.22 mW, corresponding to figures of merit (FOM) of −240.4 dB and −245.5 dB.

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Section: Multi-stage Fully-synthesizable Dtc Dtcs Have Found Extensive Usage In High Performancementioning

confidence: 99%

Section: B Nonlinearity Analysismentioning

confidence: 99%

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu

Zhang

Qiu

et al. 2021

IEEE Trans. Circuits Syst. I

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“…Analog PLL [1], [2], usually implemented with charge pump architecture, is free of quantization noise while sensitive to the PVT variations. Digital PLL [3], [4] is more attractive recently for its high PVT immunity and design portability. However, the inherent limitation caused by the gate delay barriers the further improvement of the phase noise.…”

Section: Introductionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

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“…To increase the ring-oscillator phase noise filtering bandwidth beyond the limits set by conventional PLLs, two architectures have been proposed: multiplying delaylocked loops (MDLLs) [3][4][5][6][7][8][9][10] and injection-locked phase-locked loops (IL-PLLs) [11][12][13][14][15][16][17][18][19][20]. Both architectures suppress jitter accumulation by performing a periodic realignment of the ring oscillator edges to a cleaner reference signal edge.…”

Section: Introductionmentioning

confidence: 99%

Inductorless Frequency Synthesizers for Low-Cost Wireless

Santiccioli

2021

Special Topics in Information Technology

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The quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm$$^{2}$$ 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers.

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A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique

Cited by 20 publications

References 7 publications

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Inductorless Frequency Synthesizers for Low-Cost Wireless

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