A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Rovinski, Austin; Zhao, Chun; Al-Hawaj, Khalid; Gao, Paul; Xie, Shijie; Torng, Christopher; Davidson, Scott; Amarnath, Aporva; Vega, Luis; Veluri, Bandhav; Rao, Anuj; Ajayi, Tutu; Puscar, Julian; Dai, Steve; Zhao, Ritchie; Richmond, Dustin; Zhang, Zhiru; Galton, I.; Batten, Christopher; Taylor, Michael; Dreslinski, Ronald G.

doi:10.23919/vlsic.2019.8778031

Cited by 15 publications

(4 citation statements)

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“…Prior works have described techniques for synthesizing analog blocks for UWB transmitters [8], PLLs [9], DACs [10], and other types of analog blocks [11][12][13]. This approach lowers engineering design costs, increases robustness, eases portability across PDKs, and continues to show promise even at advanced process nodes [14][15][16] 4. Analog generator flow [1] work can be likened to ASIC memory compilers that take in a specification file and produce results in industry-standard file formats, which can then be used in standard synthesis and APR tools.…”

Section: Analog Generator Architecturementioning

confidence: 99%

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Ajayi

Kamineni

Fayazi

et al. 2021

VLSI-SoC: Design Trends

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This chapter presents the world's first autonomous mixedsignal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog and mixed-signal blocks using a cell-based design methodology. The approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different planar and FinFET CMOS processes and requires no-human-in-the-loop, dramatically accelerating design time.

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Section: Analog Generator Architecturementioning

confidence: 99%

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Ajayi

Kamineni

Fayazi

et al. 2021

VLSI-SoC: Design Trends

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“…RISC-V Cores. Moreover, we have Linux-capable implementations of RISC-V processors like BlackParrot [22], ETH Zurich Ariane [29], and Berkeley Rocket [11], as well as GP-GPU-style compute throughput fabrics like HammerBlade Manycore [8] (descended from Celerity [9,14,23]), microcontrollers like Western Digital's SweRV [3], and scalable multicore server processors like the RISC-V incarnation of Princeton OpenPiton [12]. RISC-V unlocking research and education.…”

Section: Risc-vmentioning

confidence: 99%

Your agile open source HW stinks (because it is not a system)

Taylor

2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…In this way, the design/redesign time can be drastically reduced, and the RTL and place-androute (P&R) codes are friendly to be ported to another design with a different specification or process technology. Recently, this type of PLLs has been successfully incorporated into a larger synthesizable system such as processors [1], [2] and a wireless transceiver [3].…”

Section: Introductionmentioning

confidence: 99%

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

2022

IEEE J. Solid-State Circuits

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A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the threestage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO's period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO's stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM ref . The measured fundamental fractional spurs range from −56 to −45 dBc.

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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Cited by 15 publications

References 0 publications

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation

Your agile open source HW stinks (because it is not a system)

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

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