A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

Seo, Jin-Cheol; Moon, Yong-Hwan; Seo, Joon-Hyup; Jang, Jae Young; An, Taek-Joon; Kang, Jin-Ku

doi:10.5573/jsts.2013.13.3.185

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Optical Receiver and Experimental Setup1

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2016

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“…it has to cover multi data rates: 1.62, 2.7, 5.4 and 8.1 Gbps. DisplayPort also embeds the clock signal inside the data signal, so the receiver should be accompanied with clockand-data recovery (CDR) circuits [1,2]. Figure 1(a) shows the structure of the proposed optical receiver.…”

Section: Optical Receiver and Experimental Setupmentioning

confidence: 99%

A Power-adjustable Fully-integrated CMOS Optical Receiver for Multi-rate Applications

Park¹,

Yoon²,

Oh³

2016

Journal of the Optical Society of Korea

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A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has -23.7 dBm to -15.4 dBm of optical sensitivity for 10 -9 bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

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Section: Optical Receiver and Experimental Setupmentioning

confidence: 99%