For an on-chip or fully integrated microprocessor power-delivery system, the on-chip power converter must 1) be designed using the same technology as the microprocessor, 2) deliver high power density to supply a microprocessor core with small area overhead, 3) achieve high efficiency, and 4) perform fast regulation over a wide voltage range for dynamic voltage and frequency scaling (DVFS). On-chip switched-capacitor (SC) converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies [1][2][3][4][5][6].Historically, on-chip SC converters have been perceived as low power converters with output powers below 150mW [1][2][3][4][5]. However, the scalability of output power with chip area does not limit SC converters to being low power; the 1.65W maximum output power in [6] and the 840mW maximum output power presented in this paper exemplify the feasibility of high power on-chip SC converters. SC designs [1-4] utilize reconfigurable power stages for increased output and/or input voltage ranges as well as interleaving techniques to minimize the output voltage ripple, e.g., in [1], where 3.8mV pp output ripple is reported for a 41-phase interleaved SC converter. Using bulk CMOS, designs are limited in efficiency to 81% in [1] and in power density to 0.19W/mm 2 in [2]. Regarding on-chip capacitor technologies, MIM capacitors are used in a 22nm tri-gate technology in [3], and 93% efficiency is reported using ferroelectric capacitors in [4], but both designs achieve low power densities (<0.1W/mm 2 ). Employing deep trench capacitors has shown superior efficiency and power density performances, e.g., 4.6W/mm 2 at 86% efficiency for a single phase unregulated on-chip SC converter [5]. Furthermore, multi-GHz sampling frequencies are used in hysteretic control loops to achieve fast response times to transient events, e.g., 3-to-5ns response time in [3] and <1ns response time in [2]. In this paper, we utilize the deep trench capacitor and thin-oxide transistors available in 32nm SOI CMOS to design a high power (840mW) and fast response (<1ns) 16-phase interleaved reconfigurable on-chip SC converter that achieves 86.4% maximum efficiency at 2.2W/mm 2 in the 2:1 configuration and 90.0% maximum efficiency at 3.7W/mm 2 in the 3:2 configuration.The overall system diagram of the implemented SC converter is depicted in Fig. 4.7.1. Two capacitors can be configured to provide either a 2:1 or a 3:2 ideal voltage conversion ratio by toggling between a charging and a discharging state at 50% duty cycle. A 16-phase interleaving technique is employed to reduce the input current and output voltage ripples, thereby omitting the need for a dedicated output decoupling capacitor. The on-chip load consists of a programmable resistor array, which can be externally programmed by the digital configuration interface. Also the gear signal, which sets the power stage in the 2:1 or 3:2 configuration, is externally controlled. The clocked ...