2011 IEEE Energy Conversion Congress and Exposition 2011
DOI: 10.1109/ecce.2011.6064205
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A 1.65W fully integrated 90nm Bulk CMOS Intrinsic Charge Recycling capacitive DC-DC converter: Design & techniques for high power density

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Cited by 21 publications
(17 citation statements)
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“…However, the scalability of output power with chip area does not limit SC converters to being low power; the 1.65W maximum output power in [6] and the 840mW maximum output power presented in this paper exemplify the feasibility of high power on-chip SC converters. SC designs [1][2][3][4] utilize reconfigurable power stages for increased output and/or input voltage ranges as well as interleaving techniques to minimize the output voltage ripple, e.g., in [1], where 3.8mV pp output ripple is reported for a 41-phase interleaved SC converter.…”
mentioning
confidence: 84%
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“…However, the scalability of output power with chip area does not limit SC converters to being low power; the 1.65W maximum output power in [6] and the 840mW maximum output power presented in this paper exemplify the feasibility of high power on-chip SC converters. SC designs [1][2][3][4] utilize reconfigurable power stages for increased output and/or input voltage ranges as well as interleaving techniques to minimize the output voltage ripple, e.g., in [1], where 3.8mV pp output ripple is reported for a 41-phase interleaved SC converter.…”
mentioning
confidence: 84%
“…On-chip switched-capacitor (SC) converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies [1][2][3][4][5][6].Historically, on-chip SC converters have been perceived as low power converters with output powers below 150mW [1][2][3][4][5]. However, the scalability of output power with chip area does not limit SC converters to being low power; the 1.65W maximum output power in [6] and the 840mW maximum output power presented in this paper exemplify the feasibility of high power on-chip SC converters.…”
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confidence: 99%
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“…3(a) simply introduces an extra output tap via , using and four switches to actively shuttle charge from the input to the output, while are connected to the output in both phases, and act as extra decoupling capacitance. However, fully integrated designs are usually limited in the amount of flying capacitance available (1-10's for bulk CMOS [2], [3], [7], [16]), where discarding part of the flying capacitance would lead to a severe rise in switching frequency to maintain the same output impedance, especially for low conversion ratios.…”
Section: Topological Analysismentioning
confidence: 99%
“…1). To this day, this research has given us high power density designs in bulk CMOS [2], [3], even higher power densities when using exotic capacitor types such as trench capacitors [4], [5] or ferroelectric capacitors [6], designs with very fast load transients [7], [5], extremely low ripple designs [8], highly integrated designs as in [9], [10], and even in the world of discrete SMP supplies, capacitive converters are under the spotlight [11]- [13], since in theory capacitive converters can outperform inductive converters [1], [9]. Some effort has also been done to fully integrate inductive converters [14], [15], but they either require extra process steps to have access to good quality inductors, or Manuscript received November 21, 2014; revised January 16, 2015; accepted February 24, 2015.…”
Section: Introductionmentioning
confidence: 99%