A 1.7 volts operating CMOS 64K bit E/sup 2/ PROM

Wada, Yasuhiro; Maruyama,; Chida,; Takeda,; Shinada,; Sekiguchi,; Сузуки,; Kanzaki,; Yoshizawa,

doi:10.1109/vlsic.1989.1037480

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

1990

2016

Publication Types

Select...

Other3

Book2

Article1

Relationship

Self Cite0

Independent6

Authors

Journals

Cited by 7 publications

(1 citation statement)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In NAND flash memory, a high-voltage (HV) p-type MOSFET (pMOSFET) has been used as a level shifter in order to transfer voltages during program and erase operations. 1) Recently, the scaling of the NAND flash memory has increased the maximum program voltage, and the higher program voltage leads to the negatively higher gate bias of HV pMOSFETs. 2) Whenever the gate node is biased negatively, the threshold voltage of HV pMOSFET shifts and the performance of transistor is degraded.…”

mentioning

confidence: 99%

Abnormal degradation of high-voltage p-type MOSFET with n+ polycrystalline silicon gate during AC stress

Lee¹,

Joo²,

Lee³

et al. 2016

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We investigated the abnormal degradation of high-voltage p-type MOSFET (HV pMOSFET) under negative AC gate bias stress. In HV pMOSFET with n+ polycrystalline silicon (poly-Si) gate, the abnormal degradation occurs after the gradual degradation during negative AC stress. The abnormal degradation is suppressed by changing the gate material from n+ poly-Si to p+ poly-Si, and it is caused by hot holes produced by the impact ionization near the surface when electrons move from the gate toward the gate oxide. We suggest a possible mechanism to explain the improvement of degradation by using p+ poly-Si as a gate material.

show abstract

mentioning

confidence: 99%