2009
DOI: 10.1109/jssc.2009.2032634
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A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency

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Cited by 46 publications
(10 citation statements)
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“…The performance of the buffered window comparator in the back-end is tabulated in Table 2, illustrating its relative merits with respect to data rate, power dissipation, speed/power ratio, and supply voltage. To quantify the relative simulated performance of the proposed decision block with respect to published detection circuits [39][40][41][42][43][44][45][46][47][48][49], a second figure-of-merit (FOM 2 ) is defined with…”
Section: Isrn Electronicsmentioning
confidence: 99%
“…The performance of the buffered window comparator in the back-end is tabulated in Table 2, illustrating its relative merits with respect to data rate, power dissipation, speed/power ratio, and supply voltage. To quantify the relative simulated performance of the proposed decision block with respect to published detection circuits [39][40][41][42][43][44][45][46][47][48][49], a second figure-of-merit (FOM 2 ) is defined with…”
Section: Isrn Electronicsmentioning
confidence: 99%
“…This analog signal is retransmitted in a different frequency from the receiving one. The recent progress in the semiconductor process has achieved a clock speed whose inversion is near the radio frequency by using specially customized digital signal processing (DSP) devices [3,4]. If the clock speed is much faster than the inversion of Nyquist's frequency, the digital signal, which is sampled using this clock, is directly transformed into an analog signal by using a ∆Σ ∆Σ ∆Σ ∆Σ-modulation-type digital-to-analog converter (ADC) [5][6][7].…”
Section: Introductionmentioning
confidence: 99%
“…In industry grade applications presented in publications [10,11] some sort of pipelining is used along with the folding and interpolation strategy to achieve a higher resolution. As the folding order is increased the size of the necessary coarse converter increases by the same amount.…”
Section: Ormentioning
confidence: 99%
“…Thus a folding factor of 4 would require a 4-bit coarse converter. Taft et al [10] eliminate the necessity of the parallel coarse channel path by extracting the coarse information with the addition of "distributed comparators" in the folding stages. Although this strategy reduces the overall number of comparators the reduction in parallelism increases the conversion latency.…”
Section: Ormentioning
confidence: 99%
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