A 1.8 V 64.9 uW 54.1 dB SNDR 1^st order sigma-delta modulator design using clocked comparator Based Switched Capacitor technique

Abstract

Continued scaling of feature sizes have led to reduction in OpAmp gain thus making it unsuitable for using in a negative feedback system. Comparator Based Switched Capacitor (CBSC) circuits have been proposed as an alternative solution to alleviate this problem. The architecture uses continuous comparators and current sources to detect the virtual ground condition at the input rather than forcing it in the case of an OpAmp. However the architecture consumes static power due to usage of continuous comparators thus making it unsuitable for ultra low power applications. In this work, we use a clocked comparator based switched capacitor circuit technique which mitigates the power concerns by using clocked comparators instead of continuous comparators. The charge transfer phase consists of several cycles and chargingdischarging operation is performed by a number of binary weighted current sources. This work reports the application of this technique in a 1 st order ΣΔ ADC in a 0.18 μm gpdk technology and we achieve 54.1 dB peak SNDR over a 20 KHz bandwidth dissipating 64.9 μW of power from a 1.8 V supply.

A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

“…4. Comparator Architecture [17] A. Digital to Analog Converter The Digital to Analog Converter (DAC) serves two purposes in a SAR converter; it samples the input charge, and it generates an error voltage between the input and current digital estimate.…”

“…A double latch based clocked comparator [17] is chosen for implementation. The circuit diagram of the clocked comparator is shown in Fig.…”