A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB

Chen, Hua

doi:10.1088/1674-4926/33/11/115013

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2014

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“…Calibration algorithms have been proposed to compensate harmonic distortions introduced by finite opamp gain in Refs. [6][7][8][9][10][11][12] and become a mainstream.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Zhao¹,

Wei²,

Yang³

et al. 2014

J. Semicond.

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This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-m CMOS technology, this ADC occupies 10.16-mm 2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

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“…Calibration algorithms have been proposed to compensate harmonic distortions introduced by finite opamp gain in Refs. [6][7][8][9][10][11][12] and become a mainstream.…”

Section: Introductionmentioning

confidence: 99%