A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL

Abstract

Measuring a time interval in the nanoseconds range has opened the way to 3-D imaging, where additional information as distance of objects light detection and ranging (LiDAR) or lifetime decay fluorescence-lifetime imaging (FLIM) is added to spatial coordinates. One of the key elements of these systems is the time measurement circuit, which encodes a time interval into digital words. Nowadays, most demanding applications, especially in the biological field, require time-conversion circuits with a challenging combination of performance, including subps resolution, ps precision, several ns of measurement range, linearity better than few percent of the bin width (especially when complex lifetime data caused by multiple factors have to be retrieved), and operating rates in the order of tens of Mcps. In this article, we present a time-to-amplitude converter (TAC) implemented in a SiGe 350 nm process featuring a resolution of 782 fs, a minimum timing jitter as low as 1.9 ps-rms, a DNL down to 0.79% LSB-rms, and conversion rate as high as 12.3 Mcps. With an area occupation of 0.2 mm 2 [without PADs and digitalto-analog converter (DAC)], a FSR up to 100 ns, and a power dissipation of 70 mW, we developed a circuit suitable to be the core element of a densely integrated, faster and high-performance system.

Transfer Bandwidth Optimization for Multichannel Time-Correlated Single-Photon-Counting Systems Using a Router-Based Architecture: New Advancements and Results

“…The performance of the two converters, TDC or TAC, drives the choice between the two approaches. When comparing parameters such as precision, DNL, and FSR, TACs currently offer stateof-the-art performance [30] at the expense of high area and dissipated power. Our decision to use an analog approach with external TACs manufactured in a mature 350 nm technology node allows us to benefit from its state-of-the-art performance, and moves a critical element such as the time converter outside the chip containing the pixels, easing area, and power constraints.…”

“…However, a delay line must be included in each pixel of the array, limiting the maximum area and power dissipation, requirements that are typically in trade-off with jitter minimization. Thin custom-technology SPAD photodetectors typically feature a jitter of ∼30-35 ps full width at half maximum (FWHM) at room temperature [16], whereas TACs can achieve precisions down to few ps [30]. As a result, the delay line must have a low jitter, so that the dominant contribution of the system is approximately equal to that of the photodetector.…”

“…The main features of the router-based architecture can be summarized as follows: (i) the data transfer from the chip is synchronized to an external reference signal that is the laser clock, regardless of the number of pixels to be read out; (ii) the external timing circuits are dynamically and fairly shared among all pixels, thus providing efficient use of resources and no bias in the readout; (iii) the exploitation of a limited number of external timing circuits paves the way to their timing performance optimization. For example, it is possible to use a time-to-amplitude converter (TAC) that, at the expense of area occupation and power dissipation, currently provides state-of-art picosecond precision, sub-picosecond resolution, and low differential non-linearity (DNL) [30]. Given N pixels and M timing resources, the architecture can randomly choose which pixels to associate with the timing resources, for each excitation period.…”

A 4.5 ps TCSPC system for quantum sensing and imaging with superconducting nanowires

“…As can be observed, the jitter result improves by averaging subsequent samples belonging to the same conversion, until a jitter down to 4.5 ps FWHM is reached with 8 samples. This result is not traded off with other performance parameters, since under the same operating conditions a DNL of 1.5% LSB and a speed of 12 Mcps with a single sample and of 7.2 Mcps with 8 samples have been reached.…”

“…To overcome this limitation, our research focused the attention on the design of a new timing system featuring both low jitter and good performance in terms of linearity and speed. A first result has been achieved in 12 with the proposal of an ultralow jitter time-to-amplitude converter (TAC). However, the sole usage of a first-class converter does not inherently ensure the expected performance to the overall system, for the reason that most of the other components pertaining to the acquisition and conversion chain can easily play a major role in determining the timing and linearity characteristics, with the consequent risk of spoiling the good features of the selected converter.…”