A 1 G sample/s 10 b full Nyquist silicon bipolar track-and-hold IC

Baumheinrich, T.; Pregardier, B.; Langmann, U.

doi:10.1109/isscc.1997.585307

Cited by 4 publications

(3 citation statements)

References 3 publications

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“…8). This structure suppresses the metastability states, by providing more amplification of the input signal and a better conversion speed by holding a state comparison result [11][12][13].…”

Section: Sampling Stagementioning

confidence: 99%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

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Digital front-end receivers realize direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The trend is to eliminate any RF/analog mixers and digitize the RF signal as near as possible to the antenna. In order to digitize directly the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these requirements, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) which can be used as a quantizer in Continuous-Time Delta-Sigma Modulator. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sampling rate in a 0.8-2 GHz bandwidth.

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Section: Sampling Stagementioning

confidence: 99%

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Mariano

Goumballa

Dallet

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…After each comparator, two D-latches in a masterslave configuration (DFF) perform the sampling function ( Figure 5). This structure suppresses the metastability states, by providing more amplification of the input signal and better conversion speed by holding a state comparison result [7][8][9].…”

Section: Sampling Stagementioning

confidence: 99%

High-speed CMOS analog-to-digital converter for front-end receiver applications

Mariano

Boumballa

Dallet

et al. 2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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Modern front-end receivers perform direct conversion of an analog signal to digital form at intermediate frequencies (IF), simplifying the overall system design and alleviating the problems associated with IF mixers. The final aspiration is to directly digitize the RF signal and hence eliminate any RF/analog mixers. In order to direct digitize the analog input signal, a high dynamic-range and high-speed ADC is needed. Continuous-Time Bandpass Delta-Sigma Modulator can meet these specifications, using high-performance multi-bit quantizers. This article presents the design of a high-speed CMOS Analog-to-Digital Converter (ADC) to be used as a quantizer in modern digital receivers. It is designed in a 130 nm CMOS technology from STMicroelectronics. The main features of the ADC are 3-bit resolution with 4 GHz sample rate in a 0.8-2GHz bandwidth.

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“…Usually, classical technologies based on Silicon are not fast enough to work at sample rates beyond 1-2 Gsample/s [6,7]. Now, the technologies based on SiGe heterojunction bipolar transistors (HBT) offer a competitive and low cost solution for high speed design in the range of 1-10 GHz [8].…”

Section: Introductionmentioning

confidence: 99%

A 4 Gsample/s 2 bits flash ADC with 2–4 GHz input bandwidth for radio astronomy applications

David

Bégueret²,

Deval³

et al. 2006

Analog Integr Circ Sig Process

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This paper presents the design and the measurement results of a high speed A/D converter (ADC or digitizer) developed for radio-astronomy applications and especially for the ALMA (Atacama Large Millimeter Array) project. This monolithic digitizer is implemented in a BiC-MOS 0.35 µm SiGe process for high frequency mixed-signal applications. The main characteristics of this circuit are a 2 bits resolution with 3 quantization levels (equivalent to 1.5 bits) with 4 Gsample/s rate, a wide input bandwidth from 2 GHz up to 4 GHz under full Nyquist condition. The adopted digitizer architecture is that of a conventional flash analog to digital converter structure. The overall chip dissipates 652 mW under ±1.25 V supply and the die area is 5.4 mm 2 .

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A 1 G sample/s 10 b full Nyquist silicon bipolar track-and-hold IC

Cited by 4 publications

References 3 publications

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

Design of a high-speed CMOS multi-bit quantizer for continuous-time Delta-Sigma Modulator applications

High-speed CMOS analog-to-digital converter for front-end receiver applications

A 4 Gsample/s 2 bits flash ADC with 2–4 GHz input bandwidth for radio astronomy applications

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