A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

Abstract

SummaryA reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.

Time‐to‐digital converters—A comprehensive review

“…TDC has been deployed as a key component in some of the applications, namely, ADPLL, 1 ADDLL, 2 clock and data recovery (CDR) circuit, 3 time‐over‐threshold (TOT) positron emission tomography (PET), 4 jitter measurement, 5 time‐of‐flight (TOF) laser radar, 6 TOF PET scanner, 7 silicon photomultiplier SiPM PET, 8 Light Detection And Ranging (LiDAR), 9 digital storage oscilloscope, 10 fluorescence–lifetime imaging microscopy (FLIM), 11 3‐D imaging, 12 Raman spectroscopy, 13 on‐chip temperature sensor 14,15 , time domain ADCs, 16 DC–DC converter, 17 and radio frequency identification (RFID) tag sensor 18 . Earlier, TDC applications limited to high energy physics experiments and later found in ADPLL (all digital phase‐locked loop) as a phase detector.…”