A 1 GHz Alpha microprocessor

Benschneider, B.J.; Park, Sungho; Allmon, R.; Anderson, Warren; Arneborn, M.; Cho, Jang Ho; Clouser, J.; Han, Sang-Ok; Hokinson, R.; Hwang, Gyoo-Cheol; Jung, Daesuk; Kim, Jaeyoon; Krause, J; Kwack, JaeHyuk; Meier, Stephan; Seok, Yongsik; Thierauf, Stephen C.; Zhou, Catherine L.

doi:10.1109/isscc.2000.839702

Cited by 8 publications

(3 citation statements)

References 2 publications

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“…Current machines cycle between 20 and 30 FO4s per clock, and the upcoming Pentium4 microarchitecture and the aggressive Compaq/DEC Alpha chips sit at around 14 to 16 FO4s per clock [34], [35]. This may look misleading, since the Pentium4 processor, at 1.4 GHz in an 0.18 m process, would appear to have a cycle time of 714 pS and an FO4 of 90 pS, or 8 FO4s per clock.…”

Section: A Gate Delay Scalingmentioning

confidence: 99%

The future of wires

2001

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Concern about the performance of wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-m to 0.035-m feature sizes to better understand the magnitude of the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become more sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wires will remain constant if repeaters are used, meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

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Section: A Gate Delay Scalingmentioning

confidence: 99%

The future of wires

2001

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“…This microstrip line has a significantly lower inductance due to the continuous return path underneath the line. The usage of power planes in between signal layers as suggested by Gieseke [16] and Benschneider [17] thus reduces the inductance significantly beyond that due to random lines and power grids. There is an increase in the inductance below 1 GHz for the microstrip line.…”

Section: A On-chip Inductancementioning

confidence: 99%

“…Soumyanath [12] and Morton [13] use on-chip sampling to measure driver and receiver waveforms. Singer [14] and Rusu [15] refer to on-chip inductance guidelines, while Gieseke [16] and Benschneider [17] use reference planes to suppress inductance and crosstalk. Deutsch uses time-domain technique to study a wide range of structures in [18]- [20], and gives an overview of various time and frequency-domain techniques in [21].…”

Section: Introductionmentioning

confidence: 99%