A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution

Nishi, N.; Nomura, Masakatsu; Matsushita, Satoshi; Torii, Shuki; Shibayama, A.; Sakai, J.; Ohsawa, Tomoki; Nakamura, Yūichi; Shimada, Satoshi; Ito, Yoshihiro; Edahiro, Masato; Mizuno, M.; Minami, K.; Matsuo, O.; Manabe, T.; Yamazaki, T.; Nakazawa, Yasuhiro; Hirota, Yoshihiko; Yamada, Y.; Onoda, N.; Kobinata, H.; Ikeda, Makoto; Kazama, K.; Ono, Akemi; Horiuchi, Timothy K.; Motomura, Masato; Yamashina, M.; Fukuma, M.

doi:10.1109/isscc.2000.839841

Cited by 24 publications

(12 citation statements)

References 2 publications

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“…A prototype chip from NEC-Merlot-uses speculative control-driven multithreading to parallelize the execution of code that can't be parallelized by other known means. 8 We expect that more processors will make use of speculative control-driven threads in the coming decade, as this technology moves from the research phase into commercial implementations.…”

Section: Control-driven Threadsmentioning

confidence: 99%

Speculative multithreaded processors

Sohi

Roth

2001

Computer

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Speculative Multithreaded ProcessorsS emiconductor technologies-along with innovative computer architectures-have provided the bricks and mortar for building phenomenal improvements in processing speed during the past decade, culminating ultimately in the hundreds of millions of transistors used to build increasingly fast on-chip devices. Innovations in computer microarchitecture and accompanying compilers have enabled us to make good use of these building materials to provide highperformance computing systems.Typically, we decide how to use available semiconductor resources in two steps. First, we choose the desired functionality-the techniques for extracting and enhancing performance. In the implementation phase, we translate those techniques into structures and signals that we must then design, build, and verify. Although often described separately, in practice these two phases are tightly coupled.During the 1990s, novel functionality played the dominant role in processor design. Given a reasonable limit on overall design size-for example, fewer than tens of millions of transistors-we could divide up the transistor budget simply by using high-level performance metrics. Doing so made verification relatively simple, and designs did not have to explicitly account for wire delays, which were not significant compared to logic delays.In the future, implementation issues will likely dominate even basic functionality. We have begun to realize that scaling conventional superscalar designs increases complexity and cost with no guarantee that such designs will meet performance goals. Monolithic designs that use hundreds of millions of transistors will be very difficult to design, debug, and verify, and increasing wire delays will make intrachip communication and clock distribution costly. Consequently, some computer architects advocate a shift from highperformance to high-throughput processing, using distributed components that divide and conquer design process complexity and exploit communication locality to overcome wire delays. With this trend comes a renewed and increasing interest in multithreaded architectures. Such architectures can extract parallelism from a sequential program via thread-level speculation-be it control-driven or data-driven-giving them the flexibility to operate in both multiple-program, high-throughput and single-program, high-performance environments. RATIONALE FOR SPECULATIVE MULTITHREADINGFortunately, the twin goals of increasing single-program performance and decreasing implementation difficulty don't necessarily conflict. The motivation for using speculative multithreading comes from two directions: On the one hand, we are already witnessing the diminishing potential of current techniques to extract parallelism from single programs and thus increase their performance; on the other, technology trends suggest the onset of commercial processors that can simultaneously execute multiple independent threads. 1 Thus, we are almost compelled to find innovations that will enable multithreaded proce...

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Section: Control-driven Threadsmentioning

confidence: 99%

Speculative multithreaded processors

Sohi

Roth

2001

Computer

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“…Among the many studies which have proposed multithreading architectures, Multiscalar [11,3], Hydra [5,9,1], Superthreaded Architecture [14], TLDS [13,17], i-acoma [6], and Merlot [8] are representative.…”

Section: Related Workmentioning

confidence: 99%

“…The spawned thread executes code that in a sequential model would have been executed later [11,5,14,13,6,8]. This model makes possible linear ordering of threads, which simplifies the thread management and therefore the management hardware.…”

Section: Parallel Execution Modelmentioning

confidence: 99%

“…In addition, the granularity distribution of a program is biased, and the bias is different for different programs; it means that the exploitation of parallelism over a wide range of granularities will be a key to the performance of TLP architectures. While some studies have proposed speculative multi-threading architectures [11,5,14,13,6,8], those architectures have not been successful in achieving sufficient performance because they have not been able to exploit both fine-and coarse-grain parallelism.…”

Section: Introductionmentioning

confidence: 99%

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Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities

Ohsawa

Takagi

Kawahara

et al.

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)

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We propose a speculative multi-threading processor architecture called Pinot. Pinot exploits parallelism over a wide range of granularities without modifying program sources. Since exploitation of fine-grain parallelism suffers from limits of parallelism and overhead incurred by parallelization, it is better to extract coarse-grain parallelism. Coarse-grain parallelism is biased in some programs (mainly, numerical ones) and some program portions. Therefore, exploiting both coarse-and fine-grain parallelism is a key to the performance of speculative multithreading.The features of Pinot are as follows: (1) A parallelizing tool extracts parallelism at any level of granularity (e.g. even ten thousand instructions) from any program sub-structures (e.g. loops, calls, or basic blocks). The tool utilizes formulation in which the parallelization process is reduced to a combinatorial optimization problem. (2) A parallel execution model with extension of thread control instructions is designed in order to minimize the increase of the dynamic instruction count. The model employs implicit thread termination and cancellation, as well as register value transfer without synchronization. (3) A versioning cache called Version Resolution Cache (VRC) accomplishes both coarse-and fine-grained speculative multithreading. VRC operates as a large buffer for coarsegrained multi-threading. In addition, it provides low latency inter-thread communication with an update-based protocol for fine-grained multi-threading.We performed cycle-accurate simulations with 38 programs from the SPEC and MiBench benchmarks. The speedup with 4-processor-element-Pinot is up to 3.7 times, and 2.2 times on geometric mean against a conventional processor. The speedup in a program (susan) drops from 3.7 to 1.6 when the speculative buffer size is limited to 256 bytes. It confirms that exploiting coarse-grain parallelism is essential to the improved performance. FPGA implementation shows 32% overhead of area and 12% increase of critical path delay compared to a conventional processor.

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“…Section 2 describes our experimental methodology. Sections 3-10 describes our base case register file design and the seven energy saving techniques in detail: modified storage cell [7] which avoids bitline discharge for zero bits, precise read control [1,7] which avoids fetching unused operands, latch clock gating which disables latch clocks when operands are not needed, bypass skip [1,7] which turns off regfile reads when regfile bypass circuitry will supply the value, bypass R0 [7] which treats accesses to R0 separately, split bitline [7] which reduces access energy for frequently-used registers, and read-caching which avoids regfile reads when the same register is read twice in succession. In Section 11 we show how the seven techniques can be combined to yield a larger total saving, with a final reduction by a factor of 2.4 in total access energy at a cost of a 17% area increase and a 3% delay increase.…”

Section: Introductionmentioning

confidence: 99%