A 1-GSample/s 10-b full Nyquist silicon bipolar Track&amp;Hold IC

Baumheinrich, T.; Pregardier, B.; Langmann, U.

doi:10.1109/4.643652

Cited by 46 publications

(9 citation statements)

References 9 publications

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“…In [2], a TH with additional feedthrough attenuation by muting the PA in hold mode is described. The muting is done by cancelation of the PA transconductor output current by an additional transconductor current in hold mode.…”

Section: Rmo3a-3mentioning

confidence: 99%

“…Current-mode switches placed above the additional transconductor perform the clocked cancelation, resulting in a switched preamplifier (SPA) topology. Additional pedestal compensation is implemented in [2] by active feedback of the hold voltage across C H to the SPA output in hold mode. Similar circuit topologies, but without pedestal compensation, are presented in [3] and [4].…”

Section: Rmo3a-3mentioning

confidence: 99%

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A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

Buck

Berroth

Epp³

et al. 2013

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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A 0.25 µm SiGe-BiCMOS 6.4 GS/s track-andhold circuit with an input bandwidth exceeding 6 GHz and up to 2 V pp-diff input voltage range applies a hold-mode muted preamplifier that reduces signal feedthrough and improves linearity. The track-and-hold circuit provides more than 59 dBc hold-mode SFDR3 for 1.0 to 6.0 GHz 1V pp-diff input signals at 6.4 GS/s, outperforming the best commercial THs operated at only 4 GS/s.

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Section: Rmo3a-3mentioning

confidence: 99%

Section: Rmo3a-3mentioning

confidence: 99%

A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

Buck

Berroth

Epp³

et al. 2013

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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“…In order to achieve high input impedance and low output impedance, kinds of linearization techniques [1][2] have been implemented in the literature. These techniques described have their own advantages, but one common failing is that they are not generally suited to CMOS process.…”

Section: Introductionmentioning

confidence: 99%

A CMOS input buffer with linearization technique for high-speed A/D

Chen¹,

Li²,

Xu³

et al. 2015

Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering

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“…It is possible to show that the differential droop rate is mainly due to the mismatch between the base currents of Q P10 and Q N10 [20] which depends on the sampled value across C H during the hold phase. Taking into account that the order of magnitude of the current difference is proportional to the bias current, I ob1 , this latter must be kept as small as possible.…”

Section: The Output Buffermentioning

confidence: 99%

A 12-bit track and hold amplifier for giga-sample applications

Cannone

Avitabile

2015

Analog Integr Circ Sig Process

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The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 lm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 V pp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

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A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC

Cited by 46 publications

References 9 publications

A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

A CMOS input buffer with linearization technique for high-speed A/D

A 12-bit track and hold amplifier for giga-sample applications

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A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC

Cited by 46 publications

References 9 publications

A 6 Ghz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

A 6 Ghz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

A CMOS input buffer with linearization technique for high-speed A/D

A 12-bit track and hold amplifier for giga-sample applications

Contact Info

Product

Resources

About

A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS

A 6 Ghz input bandwidth 2 V_pp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 μm BiCMOS