A 1-GSPS CMOS flash A/D converter for system-on-chip applications

Yoo, Jincheol; Choi, Kyusun; Tangel, Ali

doi:10.1109/iwv.2001.923152

Cited by 36 publications

(5 citation statements)

References 8 publications

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“…As mentioned in the previous section, the major challenge in flash ADCs is the comparators and reference voltages of them causing the greatest impact power consumption, area occupation on a chip and limited speed, the second problem is the encoders' delay. Above-mentioned setbacks are conducted in a number of papers [10][11][12][13][14][15][16][17][18][19][20]. In this paper, both the above-mentioned problems are covered and a new flash ADC is presented.…”

Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

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Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

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In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

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Section: Review Of the Structure Flash Adcmentioning

confidence: 99%

“…The **threshold inverter quantisation (TIQ)-based ADC overcomes these problems. TIQ-based ADC does not require any resistor ladder; hence it is more power and space efficient [15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Approach for low power high speed 4‐bit flash analogue to digital converter

Razavi

Tavakoli

Setoudeh

2020

IET Circuits, Devices & Systems

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“…DFAL-TIQ comparators in the suggested work are judiciously selected to attain 0.065 Vstep size, which is premeditated from analog input voltage full-scale range. Premeditated step size is denoted as 1 LSB in further consideration and mathematically represented as follows [5]. 5K n = ( ) n µ n C ox (6) K p = ( ) p µ p C ox (7) HereV tn signifies threshold voltage of N MOS transistor &V tp signifies threshold voltageof P MOS transistorwhich are used for LSB calculationwhere asμ n gives the mobility of N MOS andμ p represents the mobility of P MOS and transistors respectively.…”

Section: Modified Flash Adc Designmentioning

confidence: 99%

“…3. is applied with analog input signal; trailed by identical gain booster stage to deliver the full voltage swing and improve the linearity of the system [12].Using the mathematical relation given in (5) For attaining the different quantizer levels in P MOS side (W/L) n is held in reserve at least value, at the same time, the channel widths of the P MOS transistors are speckled to curtail the flow of current during metastable region i.e. Voltage Transfer Curve (VTC).…”

Section: Modified Flash Adc Designmentioning

confidence: 99%

“…These specifications make Flash ADC the suitable choice for those devices Flash ADC is cast-off for the high-speed, low resolution applications. [1]- [5] In the suggested work, it is considered to design aThreshold-Inverter-Quantizer based on logic of energy recovery known as Diode-Free-Adiabatic-Logic(DFAL-TIQ-Comparator)for implementingAnalog-to-DigitalConverter which consumes less power. TSMC 65nm technology is used on Cadence® Virtuoso IC616 for parameter extraction.…”

Section: Introductionmentioning

confidence: 99%

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A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.

Moyal

2019

IJEAT

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Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) isdynamic component to provide connectionamongstAnalog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)usingDiode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated atpeak to peak voltage of 1.2V andcapacitive load of 1fF,results in consumption of5.53 µW of average power, which is 66.03 % lesser relative toconservative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB.Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.

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