A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface

Yuh, J.; Li, Jason; Li, Heguang; Oyama, Yoshihiro; Hsu, Cynthia; Anantula, Pradeep; Jeong, Stanley; Amarnath, Anirudh; Darne, Siddhesh; Bhatia, Sneha; Tang, Tianyu; Arya, Aditya; Rastogi, Naman; Ookuma, Naoki; Mizukoshi, Hiroyuki; Yap, Alex; Wang, Demin; Kim, Steve; Wu, Yonggang; Peng, Min; Lu, Jason; Ip, Tommy; Malhotra, Seema; Han, David K.; Okumura, Masatoshi; Liu, Jiwen; Sohn, Jung Ho; Chibvongodze, Hardwell; Balaga, Muralikrishna; Matsuda, Aki; Puri, Chakshu; Chen, Chen; V, Indra K; Chaitanya, G; Ramachandra, Venky; Kato, Yasuyuki; Kumar, Ravi; Wang, Huijuan; Moogat, Farookh; Yoon, In-Soo; Kanda, K.; Shimizu, Toshihisa; Shibata, Noboru; Shigeoka, Takashi; Yanagidaira, Kosuke; Kodama, Tetsuya; Fukuda, R.; Hirashima, Yasuhiro; Abe, Mitsuhiro

doi:10.1109/isscc42614.2022.9731110

Cited by 19 publications

(5 citation statements)

References 4 publications

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“…Most major 3D NAND memory manufacturers, such as Samsung, SK Hynix, and Micron, began to produce TLC NAND products from 2015, and competition to improve program throughput of TLC operation has started to accelerate [11]. Regarding multi-plane operation, in the middle of 2010, two-plane architecture started to be used; now, four-plane operation has become the mainstream [30][31][32]. In addition, starting from a programming time of ~800 us in 2014, current TLC NAND products are required to operate at value of less than 400 us [6], as shown in Figure 1.…”

Section: Improvement Of Program Performancementioning

confidence: 99%

“…In 2D NAND, a two-plane architecture with 8 KB page size used to be the mainstream; however, as the field moved to 3D NAND, a two-plane architecture with 16 KB page size was adopted [47]. Currently, cell under array (CuA) technology has secured space for more page buffer circuits and sense amplifiers, and so four-plane architecture with 16 KB is applied to most 3D NAND products [30,31,46,63], as shown in Figure 10a; this parallel technology contributes to higher read and program performance [70]. For further improvement, an independent multi-plane read operation is proposed, in which each group of two or four planes can perform read operations independently and asynchronously on any block/page address, thereby improving system level read and write performances [69,71,72], as shown in Figure 10b.…”

Section: Improvement Of Read Performancementioning

confidence: 99%

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A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

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Section: Improvement Of Program Performancementioning

confidence: 99%

Section: Improvement Of Read Performancementioning

confidence: 99%

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

Park

Kim

2022

Applied Sciences

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“…As a result, the power supply for IO buffers, namely VDDQ, has decreased from 3V to 1.8V and from 1.8V to 1.2V. 2.4 Gb/s IO speed was achieved in 1Tb 3D NAND Flash [15]. ONFI 1.0 NAND has one set of power supply VDD and ground VSS.…”

Section: Introductionmentioning

confidence: 99%

A Low-Power BL Path Design for NAND Flash Based on Existing NAND Interface

Makino,

Tanzawa

2024

Preprint

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This paper is an extended version of a previously reported conference paper regarding low power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, IO datapath speed increases to minimize the page access time with scaled CMOS in IOs. The power supply for IO buffers, namely VDDQ, has decreased from 3V to 1.2V, accordingly. In this paper, how a reduction in VDDQ can contribute to power reduction in BL path is discussed and validated. Conventionally, BL voltage of about 0.5V has been supplied from a supply voltage source (VDD) of 3V. BL path power can be reduced by a factor of VDDQ to VDD when BL voltage is supplied from VDDQ. To maintain a sense margin at sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison with a significant power reduction in BL path power of NAND die of about 60%. The BL path was designed in 180nm CMOS to validate the design. When the cost for powering SSD becomes quite significant especially for data center, an additional lower voltage supply such as 0.8V dedicated to BL charging for read and program verify operations may be the best option for the future.

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“…With the arrival of big data era, NAND Flash memory with large capacity, high bandwidth and high reliability is widely used, and the data transmission rate between NAND Flash memory and controller is also increasing [1,2,3,4,5,6,7,8,9,10,11,12]. Data transmission between NAND Flash memory and controller is realized by utilizing Non-Volatile double data rate (NV-DDR) interface which requires sampling data at the positive and negative edge of interface clock [1,2,3,4,5,6,7]. So the NV-DDR interface requires the interface clock with a 50% duty cycle.…”

Section: Introductionmentioning

confidence: 99%

“…The duty cycle of interface clock may be seriously distorted due to mismatches between pull-up and pull-down clock driver in the transmission path, lead to the bit error rate increase at high frequency. Therefore, NAND Flash memory needs a duty cycle corrector (DCC) to shape duty cycle of clock to 50% [1,2,3,4,5,6,7,8] , and DCC circuits with smaller correction accuracy have the more obvious advantage.…”

Section: Introductionmentioning

confidence: 99%

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

Hai,

Liu,

Wang

2024

IEICE Electron. Express

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A wide-frequency all-digital duty cycle corrector with selfadaptive configurable delay chain is proposed. The proposed circuit can detect the alterations of clock frequency and the variations of PVT, and utilizes self-adaptive feedback loop to ensure that the circuit can achieve duty cycle correction within a wide operating frequency range. The test chip is fabricated in 130nm CMOS process, the area occupies 0.016mm 2 . The chip testing results indicate that the correction error is within 2% throughout the input duty cycle from 20% to 80% at the frequency from 260MHz to 1GHz.

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A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface

Cited by 19 publications

References 4 publications

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

A Review of Cell Operation Algorithm for 3D NAND Flash Memory

A Low-Power BL Path Design for NAND Flash Based on Existing NAND Interface

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

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