A 1 Tb/s/mm² inductive-coupling side-by-side chip link

Proximity Wireless Communication Technologies: An Overview and Design Guidelines

“…To overcome these challenges, PWC is being investigated as a wireless 3D integration technology [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32] as described in Sec. I.…”

“…Contrast to the capacitive coupling, since the magnetic field is not be attenuated by the silicon substrate, multiple-chip stacking is possible with the inductive coupling. As a result, inductive coupling has been widely investigated as an PWC technology for 3D integration [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32].…”

“…In addition to drivers, many topologies exist for pre-driver, SerDes, and CDR circuits. There are two main topologies for SerDes and pre-drivers: a CML type, which is used for the CML drivers [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], and a CMOS type, which is used for the SST [46], [47] and pulse drivers [42], [44], [45]. PWC often utilizes reference-free-type CDR circuits to reduce the number of couplers.…”

“…Furthermore, the couplers can be formed in existing metal layers without requiring special processing steps, resulting in low manufacturing cost and high reliability. While a lot of initial research was focused on capacitive coupling communication technology for 2.5 and 3D integration [2], [3], inductive coupling technology was later developed to overcome challenges faced by capacitive coupling and to enable more chips to be integrated with higher stacking density [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32].…”

3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via

“…As for data communications between 3D-stacked chips, the ThruChip Interface (TCI), which uses inductive coupling, was developed. [12][13][14][15][16][17][18][19][20][21][22] Since TCI utilizes on-chip coils implemented as part of the backend-of-line process, it maintains the conventional wafer logistics and is low-cost. Furthermore, TCI has reportedly achieved higher area efficiency and lower power dissipation than TSV does.…”