A 1-V 10-bit 16.83-fJ/Conversion-step Mixed Current Mode SAR ADC for WSN

Abstract

This paper proposes a 10-bit mixed current mode low power SAR ADC for sensor node application. The different entities of a successive approximation register (SAR) analog-to-digital converter (ADC) circuit has a hybrid or mixed mode approach i.e.,voltage mode regenerative comparator; mixed SAR logic; and current mode digital-to-analog converter (DAC). The performance limitation of speed and the kick-back noise of a dynamic comparator is resolved using duty cycle controlled regenerative comparator. A mixed mode logic of a SAR is partitioning the design into synchronous ring counter and asynchronous output register. The data shifting of a ring counter is with the common clock tick while the output register exchanged it asynchronously using handshake signals, resulting in a low power SAR. The current mode switching function in a DAC to reduce asynchronous switching effect resulting in a low energy conversion per step. In overall, the proposed mixed SAR ADC consumes a 41.6 W  power and achieves an SFDR 69.3 dB at 10 MS/sec and 1 V supply voltage. It is designed and simulated in the 0.18  m TSMC CMOS process. Index Terms-Successive approximation register (SAR), mixed-mode, current-mode, regenerative-comparator, analog-to-digital-converter (ADC), digital-to-analog converter (DAC).

Impact of Equalizer step size in Underwater Acoustic Communication Channel

“…In this, a least square technique [8] and low order DFE [9] are used for the channel estimation for single carrier spread spectrum sequence. For MIMO acoustic communication, DFE [10,11], Low Density Parity Code (LDPC) [12], Y shaped antenna was designed for UWB applications [13], Normalized Least Mean Square algorithm [14] and gradient-based LMS algorithm [15], Low power SAR ADC for wireless sensor node was designed [16]. The computational complexity is reduced by restricting the length of training pulse less than the number of taps used in the equalizer.…”