A 1-V CMOS D/A converter with multi-input floating-gate MOSFET

Wong, Leon; Kwok, Chee Yee; Rigby, G.A.

doi:10.1109/4.792610

Cited by 16 publications

(13 citation statements)

References 15 publications

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“…The strategy for OTA-based circuits and systems places far greater emphasis on custom design, optimization, and control of the OTA-parameters [1]. Although a number of CMOS DACs have been published [2][3][4], they have complex circuit structure.…”

Section: Introductionmentioning

confidence: 99%

An 8-Bit 50-MS/s CMOS Digital-Analog Converter

Mınaeı

Turkoz

2004

Analog Integrated Circuits and Signal Processing

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Section: Introductionmentioning

confidence: 99%

An 8-Bit 50-MS/s CMOS Digital-Analog Converter

Mınaeı

Turkoz

2004

Analog Integrated Circuits and Signal Processing

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“…To implement a 'measure-all-adjust-all strategy', area-efficient DAC arrays are required. A typical application of DAC arrays is given by the coefficient update of decision-feedback equalisers in high-speed serial links [1].Previous work that implemented dynamic DACs based on floatinggate transistors [2] or current memory cells [3] primarily focused on device mismatch elimination in single DACs [4], rather than on the application of distributed DAC arrays as in our work. The novelty of this work is related to the dynamic operation based on deep-trench capacitors that allow the design of ultra-small DAC array cells.…”

mentioning

confidence: 99%

Small-area, periodically-refreshed DAC array in 45 nm SOI CMOS

Kossel

2010

Electron. Lett.

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A small-area digital-to-analogue converter (DAC) in 45 nm SOI CMOS technology is presented that is based on a centrally located, static current-mode DAC, the output current of which is fed to an array of distributed, dynamically-refreshed small-area DACs. Owing to the dynamic operation of the distributed DACs, a single array element can be made as small as 8 × 8 mm. The measured retention time of a single array element with 7-bit resolution is 3 ms at a temperature of 1258C.Introduction: The large number of available transistors in modern technologies allows circuit designers to build ever more complex circuits with an increasing number of adjustable coefficients and parameters. To implement a 'measure-all-adjust-all strategy', area-efficient DAC arrays are required. A typical application of DAC arrays is given by the coefficient update of decision-feedback equalisers in high-speed serial links [1].Previous work that implemented dynamic DACs based on floatinggate transistors [2] or current memory cells [3] primarily focused on device mismatch elimination in single DACs [4], rather than on the application of distributed DAC arrays as in our work. The novelty of this work is related to the dynamic operation based on deep-trench capacitors that allow the design of ultra-small DAC array cells.

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“…Low power consumption is the most important criteria in designing the IC [1]. It is very well known that reducing the supply voltage is one of the most effective ways to reduce power consumption [2] [3]. Lowering the operating voltage puts harder constraints on the analog circuits, as lower voltages are available to drive the transistor.…”

Section: Introductionmentioning

confidence: 99%

Leakage current cancellation technique for low power switched-capacitor circuits

Wong

Hossain

Walker

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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In this paper, we describe a circuit technique to implement low power switched-capacitor circuits for low frequency operation. Low power consumption is crucial for medical implant devices. Reducing supply voltage is well known to minimize power dissipation. To facilitate low voltage operations, the transistor's Vth are becoming lower and lower. Low Vth transistors have high leakage currents which impact the performance of switchedcapacitor circuits, sample-and-hold amplifiers and many more. A new circuit technique is presented here to largely minimize the effective leakage current when the CMOS switch is turned off. It employs an active feedback loop to automatically cancel both junction and sub-threshold channel leakage. By reducing the effective leakage current, the capacitors used in the circuit can be significantly reduced, hence lowering the overall power consumption. This is a general technique and can be used in various circuit applications KeywordsLow power, analog, leakage current, switched-capacitor circuit, sample and hold, amplifier.

show abstract

A 1-V CMOS D/A converter with multi-input floating-gate MOSFET

Cited by 16 publications

References 15 publications

An 8-Bit 50-MS/s CMOS Digital-Analog Converter

An 8-Bit 50-MS/s CMOS Digital-Analog Converter

Small-area, periodically-refreshed DAC array in 45 nm SOI CMOS

Leakage current cancellation technique for low power switched-capacitor circuits

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