A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing

Zhang, H.; Prabhu, V.; George, Varghese; Wan, M.; Benes, M.; Abnous, A.; Rabaey, Jan M.

doi:10.1109/4.881217

Cited by 84 publications

(35 citation statements)

References 8 publications

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“…DPM policies provide the control algorithms for state transitions. 12 Transitions among states have a finite delay penalty, even when changing the operation frequency. Thus, identifying the policies that maximize performance under energy constraints or that solve the dual problem may be computationally complex.…”

Section: System Softwarementioning

confidence: 99%

“…Thus, identifying the policies that maximize performance under energy constraints or that solve the dual problem may be computationally complex. 12 We envision at least two operating modes for SoCs with many power-manageable components. In one mode, the system software running on a power-manageable component determines its state transitions, based on the system state and its workload.…”

Section: System Softwarementioning

confidence: 99%

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Networks on chips: a new SoC paradigm

2002

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Section: System Softwarementioning

confidence: 99%

Section: System Softwarementioning

confidence: 99%

Networks on chips: a new SoC paradigm

2002

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“…They use the dynamic reconfigurability of field-programmable gate arrays to exploit power and performance efficiency. The PLEIADES project at UC Berkeley [21] proposes an interconnection of a low power FPGA, datapath units, memory, and processors, optimized for different application domains. The Pleiades researchers conclude that a hierarchical generalized mesh interconnect structure [22] is most appropriate for their architecture because it balances both the global and the local interconnect.…”

Section: Related Workmentioning

confidence: 99%

Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

Oliver

Rao

Sultana

et al. 2005

Power-Aware Computer Systems

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Abstract. Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design in tuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based embedded architecture targeted for multi-rate signal processing applica tions.We present a preliminary design of the Synchroscalar architecture and some design space exploration in the context of important signal process ing kernels. In particular, we find that synchronous design and substan tial global interconnect are desirable in the low-frequency, low-power do main. This global interconnect enables parallelization and reduces pro cessor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.

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“…Even though it may be possible to implement MPEG4 onto a homogeneous fabric, there is a significant risk of either under-utilizing many tiles and links, or, at the opposite extreme, of achieving poor performance because of local congestion. These factors motivate the use of an application-specific on-chip network [15].…”

Section: Figure 1 Homogeneous Cmps and Heterogeneous Soc Applicationsmentioning

confidence: 99%