A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

Tsai, Jen-Huan; Ko, Sheng-An; Wang, Chia‐Wei; Yen, Yang-Chi; Wang, Hui-Huan; Huang, Po-Chiun; Lan, Po-Hsiang; Shen, Meng-Hung

doi:10.1109/jssc.2015.2465853

Cited by 28 publications

(14 citation statements)

References 33 publications

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“…It can be observed from Table V that the proposed solution achieves the best performance. It should be noted, however, that solutions [6] and [22] show higher quiescent current due to some auxiliary analog and digital circuits related to the specific application.…”

Section: Simulation Results and Comparisonmentioning

confidence: 99%

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

2021

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Targeting the more recently adopted low-power memories for data-logging operation in IoT nodes, this paper presents a simple reconfigurable dual-branch cross-coupled charge pump (CP) topology in which clock amplitude scaling and modulation of the number of stages are exploited to improve power efficiency and/or change the output voltage without degrading speed performance. The proposed solution allows a reduction of the power conversion losses, maintaining speed, maximum output voltage and silicon area unaltered as compared to the conventional charge pump. Post-layout simulation results confirm the effectiveness of the proposed topology which can be adapted to any other kind of linear charge pump.

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Section: Simulation Results and Comparisonmentioning

confidence: 99%

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

2021

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“…Table II lists the performance comparisons among our regulated charge pump with the prior works [12,13,30,31], which are capable of producing output voltages to higher than twice the supply voltage (i.e., V OUT > 2VDD). The proposed RCP is realized by CMOS charge pump with bulk switching technique to achieve high power efficiency [14].…”

Section: Experiments Resultsmentioning

confidence: 99%

“…And the needs of small chip area and ultra-low power eNVMs, which increases battery lifetime and reduces the cost, have become the key design aspects for portable equipment and internet-of-things (IoT) [7,8,9]. As a result, the advanced pump structures with smaller size and higher efficiency have been extensively researched [10,11,12,13,14,15,16,17,18,19]. Meanwhile more attentions are paid to the regulation techniques [20,21,22,23,24,25] or the clock inputs [26,27,28,29,30,31] of charge pumps, since the regulation and clocking schemes have also become more and more crucial to reduce power and chip size of pump system [4,22].…”

Section: Introductionmentioning

confidence: 99%

A charge pump system with new regulation and clocking scheme

Zhu

Jiang

Lin

et al. 2019

IEICE Electron. Express

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A novel charge pump system with new regulation and clock generating techniques is proposed and verified in a 0.13 µm CMOS process. Rather than generating the reference voltage by band-gap reference (BGR) and the detected voltage by high voltage divider in the conventional regulation, both voltage reference and division of proposed pump system are implemented by single new circuit. Besides, the conventional oscillator for clock input of charge pump system is removed while an adaptive clock generation scheme is introduced to reduce the power consumption and shrink the system size. The experiment results show that the pump system can produce a stable and smooth output with a small ripple, and the high output accuracy is comparable to the conventional solution equipped with BGR. Moreover, the power consumption of the pump controlling is reduced by about 80% while the size of pump system is decreased by about 25%. Therefore, the proposed regulated charge pump (RCP) is very suitable for ultra-low power and high precision applications, for example, the embedded nonvolatile memories (eNVMs).

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“…The work in [10] showed that, for high-voltage charge pumps (e.g., V out > 2V dd ), the output ripple and efficiency of a charge pump can be improved by using complementary charge-pump structures, and simulated ripples of 65-73 mV were achieved. The charge pumps of [11,12] leveraged closed-loop structures to achieve ripple voltages in the tens-of-millivolts range; however, closed-loop operation does not guarantee low ripple voltages [13,14].…”

Section: Charge-pump Backgroundmentioning

confidence: 99%

A Regulated Charge Pump with Extremely Low Output Ripple

Navidi

Graham

2019

Electronics

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In this paper, we present a regulated charge pump with extremely low output ripple (<1 mV) that can be used for accurate programming of nonvolatile memory. We present a technique to include a low-drop-out regulator inside the charge-pump regulation loop to reduce the ripple. This charge pump was fabricated in a 0.35 μ m standard CMOS process. The die area of this charge pump is 0.163 mm 2 . While operating from a 2.5 V supply, this charge pump generates regulated voltages up to 10 V.

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A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics

Cited by 28 publications

References 33 publications

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes

A charge pump system with new regulation and clocking scheme

A Regulated Charge Pump with Extremely Low Output Ripple

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