A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

Huang, Guan-Ying; Chang, Soon-Jyh; Liu, Chun-Cheng; Lin, Ying-Zu

doi:10.1109/jssc.2012.2217635

Cited by 131 publications

(72 citation statements)

References 17 publications

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“…Figure 5 shows the circuit of 8-bit charge redistribution DAC. To meet the requirement of full-swing input, only one sampling capacitor ( s) of 32 times unit capacitor is adopted [10].…”

Section: Circuit Designmentioning

confidence: 99%

A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

Chen

Yang

2018

Journal of Electrical and Computer Engineering

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A mixed-signal programmable Time-Division Power-On-Reset (TD-POR) circuit based on 8-bit Successive Approximation Analog-to-Digital Converter (SAR ADC) for accurate control in low-power hearing-aid System on Chip (SoC) is presented in this paper. The end-of-converter (EOC) signal of SAR ADC is used as the mode-change signal so that the circuit can detect the battery voltage and volume voltage alternately. And the TD-POR circuit also has brown-out reset (BOR) detection capability. Through digital logic circuit, the POR, BOR threshold, and delay time can be adjusted according to the system requirement. The circuit is implemented in SMIC 0.13 m 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. The detection resolution is the best among previous work. With 120 Hz input signal and 15 kHz clock, the ADC shows that Signal to Noise plus Distortion Ratio (SNDR) is 46.5 dB and Effective Number Of Bits (ENOB) is 7.43 bits. Total circuit power consumption is only 86 w for low-power application.

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“…Figure 5 shows the circuit of 8-bit charge redistribution DAC. To meet the requirement of full-swing input, only one sampling capacitor ( s) of 32 times unit capacitor is adopted [10].…”

Section: Circuit Designmentioning

confidence: 99%

A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

Chen

Yang

2018

Journal of Electrical and Computer Engineering

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“…Therefore, energy efficiency is a critical challenge for ADCs design. This paper [6] presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window.…”

Section: IImentioning

confidence: 99%

A Review Paper on A 10 Bit, Low Power ADC Suitable for Wireless Application

Fulzele¹,

Patra²

2015

International Journal of Innovative Research in Electrical, Ele

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This Paper presents the Design of analog to digital converter(ADC) for wireless applications, so here is the selection of right architecture is very crucial. We have chosen successive approximation Analog to Digital Converter because of their compact circuitry as compared with the Flash ADC which makes this SAR ADC inexpensive. Day By Day more and more applications are built on the basis of power consumption so this SAR ADC will be useful for high speed with medium resolution and low power consumption. The Successive Approximation (SAR) architecture is very suitable for data acquisition, it has resolutions ranging from 8 bits to 12 bits and sampling rates ranging from 50 KHz to 50 MHz.

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“…The burst-like property of the signal indicates that traditional successive approximation algorithm, which always starts conversion from the MSB and continues towards the LSB, may not be efficient enough compared to signal-activity-based algorithms [77,78]. In [77], the ADC selects switching sequences to skip several conversion steps when the signal is within a predefined small window. In [78], the ADC uses a previous conversion result as the initial guess of the current sample and bit-cylces the LSBs first.…”

Section: Future Directionsmentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

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A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

Cited by 131 publications

References 17 publications

A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

A Review Paper on A 10 Bit, Low Power ADC Suitable for Wireless Application

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

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