A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS

Sahani, Jagdeep Kaur; Singh, Anil; Agarwal, Alpana

doi:10.1007/s00034-021-01861-z

Cited by 3 publications

(5 citation statements)

References 28 publications

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“…The 3-bit flash TDC with 3 ps resolution is used in the present work. The resolution is 50% finer in the present work as compared to the work in Sahani et al 26 Architecture-wise, both designs are different. In terms of measurable results, the present work achieves a 72% reduction in the jitter and 16% reduction in the power consumption as compared to the former work.…”

Section: Discussioncontrasting

confidence: 70%

“…Though proposed ADPLL has more jitter as compared to other designs, 17,25 it has lower power consumption and locking time. The work reported in Sahani et al 26 and present work have different architectures. The dual-loop architecture with two TDCs (4-bit Vernier and 4-bit flash), VCO, and digital filter is used in Sahani et al 26 The 4-bit flash TDC is calibrated using the LMS algorithm to achieve low PVT ADPLL.…”

Section: Discussionmentioning

confidence: 74%

“…The work reported in Sahani et al 26 and present work have different architectures. The dual-loop architecture with two TDCs (4-bit Vernier and 4-bit flash), VCO, and digital filter is used in Sahani et al 26 The 4-bit flash TDC is calibrated using the LMS algorithm to achieve low PVT ADPLL. The resolution of 4-bit flash TDC is 6 ps.…”

Section: Discussionmentioning

confidence: 74%

“…The PVT variation in periodic jitter without calibration for ADPLL is shown in Figure 7. The total variation of 22.9% is 17 Tao and Heng 22 ur Rahman et al 23 Yan et al 24 De Caro et al 25 Sahani et al 26 Supply voltage (V) observed in the ADPLL without calibration. The proposed 3-bit flash TDC with resolution of 3 ps and periodic jitter of 0.46 ps is used.…”

Section: Adpll Simulation Resultsmentioning

confidence: 99%

See 3 more Smart Citations

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

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Section: Discussioncontrasting

confidence: 70%

Section: Discussionmentioning

confidence: 74%

Section: Discussionmentioning

confidence: 74%

Section: Adpll Simulation Resultsmentioning

confidence: 99%

See 2 more Smart Citations

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

Self Cite

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show abstract

“…Calibration schemes in time-to-digital converters (TDC) usually involve multiple delay cells [1,2] and digital circuits to perform calibration algorithms [3,4] based on PLL phase error information. Using time-difference amplifiers (TA) in TDC can achieve sub-gate-delay resolution while maintaining performance tradeoffs, such as resolution, power, and area consumption.…”

Section: Introductionmentioning

confidence: 99%

Process and temperature robust time‐difference amplifier with analog calibration

Melo‐Pinzón

Flores‐Verdad

2022

The Journal of Engineering

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An analogue calibration CMOS circuit for a time‐difference amplifier is presented and compared over a digital calibration scheme in terms of process and temperature variations. Time‐difference amplifiers (TA) are used in time‐to‐digital converters (TDC) for improving conversion resolution. In TA‐based TDC, global variations (process, temperature, and voltage) are dominant over local variations (mismatch) if analogue approaches are used over the digital ones, where the matching between many cells is highly required. Unlike the digital calibration circuit, the proposed analogue approach based on a charge pump improves the TA gain performance against process and temperature variations. The simulations of the proposed TA in a 180 nm CMOS technology showed a 12% reduction in process and temperature variations with a maximum power consumption of 130 μW at 100 MHz operation frequency.

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A 3-6GHz Fast Locking ADPLL Based on Charge-Steering-Sampling Technique

Zhang,

Hu,

et al. 2024

2024 6th International Conference on Electronic Engineering and Informatics (EEI)

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A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS

Cited by 3 publications

References 28 publications

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Process and temperature robust time‐difference amplifier with analog calibration

A 3-6GHz Fast Locking ADPLL Based on Charge-Steering-Sampling Technique

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