A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor

Abstract

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.

A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation

“…It can be seen that the enhancement of the capacitive array DAC switching scheme can reduce the overall energy consumption of the chip. Compared with the conventional capacitive array DAC structure [ 13 ], the energy consumption of the set-and-down DAC structure can be reduced by 81.26% [ 14 ]; that of the C-2C common-mode voltage DAC structure can be reduced by 90.61% [ 15 ]; that of the three reference voltages, an additional reference voltage, V cm , and the switching scheme (tri-level) DAC structure can be reduced by 96.89% [ 16 ]; that of the common-mode voltage monotonic (VMS) DAC structure can be reduced by 97.66% [ 17 ]; that of a perfect application of V cm and the monotonic technique (hybrid) DAC structure can be reduced by 98.83% [ 18 ]; and that of the capacitor-splitting structure, charge-average switching technique, and V aq (equal to V ref /4) (VQS) DAC structure can be reduced by 98.10% [ 19 ], and two sub-capacitor arrays with the common-mode DAC structure (TSC) can be reduced by 98.45% [ 20 ].…”

“…These DAC schemes greatly reduce the energy consumption of the DAC structure, but these structures include at least three reference voltages, which increase the overall circuit complexity of the SAR ADC and thus the energy consumption of the other modules; they even cause a common-mode voltage shift [ 14 , 15 , 16 , 17 , 18 , 19 ]. Compared to [ 20 ], the proposed scheme does not require a third reference voltage and is 9-10-bit adjustable. In order to reduce the overall circuit complexity and power consumption of the SAR ADC, a low-complexity capacitor array DAC switching scheme with one-LSB common-mode voltage variation for SAR ADC was designed; it applies bridge switches and the floating technique to reduce DAC switching energy.…”